Siemens brings ReadyStart RTOS to RISC-V
Siemens has expanded its Nucleus ReadyStart program to the RISC-V architecture.
Siemens has expanded its Nucleus ReadyStart program to the RISC-V architecture.
Synopsys and Analog Devices have agreed to provide model libraries for the chipmaker’s DC/DC ICs and power regulators that work with the Saber simulation tool.
Recognizing the 75th anniversary of the transistor in December, the 68th IEDM has taken on the theme of looking at “transformative devices to address global challenges”.
Real Intent has extended the fault coverage of its Meridian DFT static sign-off tool with improvements to the reporting of issues and the ability to track down root causes.
DAC returns to San Francisco in July for its 59th year as a purely in-person event.
Variable lifetimes are an apparently basic but also tricky feature within the verification language.
DVCon Europe will be held as a live event in Munich in early December.
Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.
The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
Nvidia says it will support the UCIe chiplet interface standard once it has “stabilized” while opening up its latest form of NVLink to other companies.