FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
The encryption chain for today's highly collaborative designs needs to be managed with care.
Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.
What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
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