Mick Posner |  December 16, 2013
Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.
Tim Whitfield |  August 25, 2013
What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
Dan Benua |  July 25, 2013
Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
Graham Bell |  July 3, 2013
Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
Neel Desai |  May 30, 2013
How to speed project start-up, boost designer productivity and increase schedule predictability using design management tools.
Graham Bell |  May 14, 2013
RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
Mick Posner, Synopsys |  April 24, 2013
Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Michael Sanie, Synopsys |  April 4, 2013
Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
Steve Pateras |  November 16, 2012
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.