Using HAPS to streamline IP to SoC integration
The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
Expert Insights
Consistency key to gaining the advantages of IP integration
Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.
Proving the 20nm ecosystem with the ARM Mali GPU
What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
Formal techniques tackle the SoC verification challenge
Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
The challenge of clock domain crossings – and some solutions
Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
Enabling greater productivity and schedule predictability in IC design
How to speed project start-up, boost designer productivity and increase schedule predictability using design management tools.
Building an RTL sign-off flow
RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
IP-to-SoC prototyping demands consistency
Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Debugging the debug challenge
Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
IJTAG: delivering an industry platform for IP test and integration
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
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