process optimization


August 16, 2018

IBM and Synopsys to apply DTCO to post-finFET process development

Collaboration on DTCO offers IBM a better way to evaluate combinations of transistor architectures, materials and other process technology innovations using design metrics, before real wafers become available for physical experimentation.
March 23, 2018

Layout schema generation speeds early-stage yield learning

LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors