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IP
Accellera sets up group for one-stop verification stimulus
Accellera has set up a working group to develop a language-independent way of capturing and managing test stimuli that can be used across a wide range of verification environments.
ARM to upgrade smartphone processing with Cortex-A72 combination
ARM has launched a 64bit processor core aimed at high-end mobile phones, coupled to a new graphics processor and cache-coherent interconnect.
ARM to provide safety docs for real-time processors
ARM has picked up TÜV Süd certification for a version of its C compiler and produced an ISO 26262 documentation pack for the Cortex-R5 processor
Cadence updates Xtensa with memory and power saving features
Cadence Design Systems has launched the 11th generation of Tensilica Xtensa customizable processors, with changes for VLIW, power-saving caches and memory accesses.
Use-cases drive high-level verification tool
Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.
10Gbit/s USB 3.1 IP and verification support on the way
USB 3.1 IP, verification IP, virtual development kit build on Synopsys' USB 3.0 DesignWare and supporting ecosystem
ARC core focuses on embedded Linux applications
Synopsys updates ARC core to improve support for embedded Linux and other advanced operating systems such as Android
Minimal 32bit IP cores tackle connected devices market
Minimal IP cores are meant to serve broader market than IoT, using revised instruction set to increase code density, save on chip memory and enable security
Carbon introduces exchange for building and stressing virtual prototypes
Carbon Design Systems has introduced a web portal to streamline the process of finding the most appropriate executable models for a system-level virtual prototype.