How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
Many IoT applications have a very strict energy budget. SoC designers targeting the IoT have to trade off providing the features that the market demands with the power budget the applications demand. What are their options?
Using triple modular redundancy, error detection and correction, and 'safe' FSMs to ensure greater functional safety in FPGA-based designs
Established physical layer verification IP packages focus so much on protocols they miss problems that arise from the broader context. A PHY verification kit bridges the gap.
Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
How Imagination Technologies used FPGA-based prototyping to develop its GPU IP and integrate it into a real world system
How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices
A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
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