Established physical layer verification IP packages focus so much on protocols they miss problems that arise from the broader context. A PHY verification kit bridges the gap.
Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
How Imagination Technologies used FPGA-based prototyping to develop its GPU IP and integrate it into a real world system
How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices
A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
A look at a tool and a flow that makes it easier to put designs on to a HAPS physical prototyping system for verification, debug and software development purposes
FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.
IC designers are becoming increasingly worried about the possibility of third parties inserting malicious 'trojan' circuitry into their ICs.
The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
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