Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
One roadblock to the integration of IP from multiple vendors into an SoC is the likelihood of finding duplicate cell names in the merged design. Carefully considered renaming strategies can fix the problem without causing design database bloat.
The promise of autonomous vehicles is driving profound changes in the design and testing of automotive ICs.
Portable Stimulus allows reuse along horizontal, vertical and technique axes, but you need to be aware of the strengths and weaknesses of each to get the greatest benefits.
The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
Application-specific processors can provide high performance for specialised tasks at low energy cost.
How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.
Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
Artificial intelligence and machine learning require the performance and flexibility offered by embedded FPGA (eFPGA) technology.
View All Sponsors