Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis
Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Making a smooth transition to IJTAG, the scan-test strategy for IP blocks, without having to change your existing hardware.
The article is abstracted from a presentation given at NASCUG by Umesh Sisodia and originally developed by Ashwani Singh of CircuitSutra Technologies on how to create adaptors between various modeling abstraction levels in SystemC.
Simulation speed is a key issue for the virtual prototyping (VP) of multiprocessor system-on-chips (MPSoCs). The SystemC transaction level modeling (TLM) 2.0 scheme accelerates simulation by using interface method calls (IMC) to implement communication between hardware components. Acceleration can also be achieved using parallel simulation. Multicore workstations are moving into the computing mainstream, and symmetric [...]
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