DFT

January 26, 2023
3D IC workflow democratization

Give the people what they want: toward making 3D IC mainstream

Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
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April 25, 2022
Wu Yang is the technical project management director for Tessent design-for-test products at Siemens EDA.

Toward usable and scalable DFT for 3D IC design

Both 3D IC and 2.5D IC techniques are being used on more designs and the DFT infrastructure is evolving to meet the challenges they pose.
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March 22, 2021

Silicon lifecycle solutions help you listen to your chip

SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
March 2, 2021
streaming scan network featured image

Streaming Scan Network technology delivers ‘no compromise’ DFT for AI designs

A new technique is especially efficient for AI chips with modular, tiled design strategies leveraging multiple instantiations of the same cores.
August 27, 2020
total critical area feature - headline image

How to optimize test patterns based on critical area

The world of ATPG just changed with the introduction of a new way to create and choose the most effective test patterns.
July 28, 2020
Jay Jahangiri, Product Manager for Mentor, a Siemens Business

Catch the next wave in DFT automation

It is easier than ever to build a flexible, resilient, and end-to-end hierarchical DFT flow with smart automation.
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April 24, 2020
Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. He is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society, and a Senior Member of the IEEE.

How to gain a competitive edge with advanced DFT

Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
November 7, 2019
Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. He is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society, and a Senior Member of the IEEE.

International Test Conference celebrates 50 years of advancing test technology

It's the fiftieth International Test Conference this year. How much has been achieved and how much more work is there to do to ensure that we can keep building chips that do what they are supposed to?
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September 13, 2019
John Blyler is a Consulting Editor of Tech Design Forum and the Editor-in-Chief of Interference Technology. He spent the first half of his career as a hardware-system systems engineer and program managerand the second half as a technology journalist, science writer and educator. John is an affiliate professor of systems engineering at Portland State University and lecturer for UC-Irvine’s online IoT program.

AI firsts (and more) at America’s SEMICON

SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
August 15, 2019
Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. He is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society, and a Senior Member of the IEEE.

Achieving more efficient hierarchical DFT for Arm subsystems

Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
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