DFT

February 29, 2024
TCP-Net Featim

TCP-Net and TCP-Net++ – a revolution in regression testing

TCP-Net is Test Case Prioritization using End-to-End Deep Neural Networks and addresses the challenges of today's software-rich projects.
Article  |  Tags: , , , ,   |  Organizations:
February 29, 2024

The keys to ensuring IC quality

How the latest DFT techniques pave the way for quality and success for today's advanced designs.
Article  |  Tags: , , , , , , ,   |  Organizations: ,
February 8, 2024
Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. He is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society, and a Senior Member of the IEEE.

How AI improves DFT, test and yield

Take a high level view of the AI strategies used within the Tessent family to improve across-the-board performance.
August 8, 2023
Jeff Wilson is a Product Management Director for DFM applications in the Calibre Design solutions organization at Siemens Digital Industries Software. Before joining Siemens, Jeff worked at Motorola and SCS. He holds a B.Sc. in design engineering from Brigham Young University and an MBA from the University of Oregon.

Improved power management and faster time to market?

We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
Expert Insight  |  Tags: , , , , ,   |  Organizations:
May 30, 2023
IJTAG standards progress - featured image

Refreshing the IEEE 1687 IJTAG family for today’s designs

Learn more about how the IJTAG family and associated standards are being enhanced for current challenges.
Article  |  Tags: , , ,   |  Organizations:
January 26, 2023
3D IC workflow democratization

Give the people what they want: toward making 3D IC mainstream

Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
Expert Insight  |  Tags: , , , , ,   |  Organizations:
April 25, 2022
Wu Yang is the technical project management director for Tessent design-for-test products at Siemens EDA.

Toward usable and scalable DFT for 3D IC design

Both 3D IC and 2.5D IC techniques are being used on more designs and the DFT infrastructure is evolving to meet the challenges they pose.
Expert Insight  |  Tags:   |  Organizations:
March 22, 2021

Silicon lifecycle solutions help you listen to your chip

SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
March 2, 2021
streaming scan network featured image

Streaming Scan Network technology delivers ‘no compromise’ DFT for AI designs

A new technique is especially efficient for AI chips with modular, tiled design strategies leveraging multiple instantiations of the same cores.
August 27, 2020
total critical area feature - headline image

How to optimize test patterns based on critical area

The world of ATPG just changed with the introduction of a new way to create and choose the most effective test patterns.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors