Unified Power Format (UPF)
What is UPF?
The Unified Power Format (UPF) is a published IEEE standard and developed by members of Accellera. It is intended to ease the job of specifying, simulating and verifying IC designs that have a number of power states and power islands. The most recent officially published version is IEEE 1801-2013.
What does it do?
UPF is designed to reflect the power intent of a design at a relatively high level. UPF scripts describe which power rails should be routed to individual blocks, when blocks are expected to be powered up or shut down, how voltage levels should be shifted as signals cross from one power domain to another and whether measures should be taken to retain register and memory-cell contents if the primary power supply to a domain is removed.
How is it put into action?
The backbone of UPF, as well as the similar Common Power Format (CPF), is the Tool Control Language (Tcl), a scripting language originally created to provide a way to automate the control of design software.
The attraction of Tcl is that command-line commands can be used as statements in a script. Most Tcl implementations are specific to an individual tool. However, the CPF and UPF definitions are unusual in that they are meant to be used with all tools in a power-aware flow – the tools themselves have to determine whether the commands supplied in the Tcl script are relevant to them or not.
The Tcl command “create_power_domain”, for example, is used by UPF-aware tools to define a set of blocks in the design that are treated as one power domain that is supplied differently to other blocks on the same chip. The idea behind this type of command is that power-aware tools read in the description of which blocks in a design can be powered up and down independently. The tools can use that information to determine, for example, how a simulation will behave under different conditions.
For example, a testbench written in SystemVerilog may identify to the simulator that a particular block should be powered down to ensure that other blocks do not access it without checking on power status first.
A transistor-level simulation may use the power definitions to see what happens when supply voltages or substrate bias voltages change. Do all the necessary logic paths meet expected timing when the supply voltage to one block is lowered to save power while others are running at their maximum voltage? Similarly, a static analysis tool may check that the correct level shifters are in place to determine whether blocks in different power domains can communicate.
Who supports it?
A number of EDA vendors have chosen to support UPF in their flows, including Mentor Graphics and Synopsys. However, support is not universal. Cadence Design Systems supports the Common Power Format originally developed by the company but which is now administered by the Silicon Integration Initiative but has declared support for the latest version of IEEE 1801, which incorporates a number of features from CPF.