Clock domain crossing

IC designs with multiple clock domains are now commonplace. They make it possible to optimize for power by varying clock frequency and voltage as well as for timing by removing the need to distribute a single, low-skew clock to all parts of a design. The problem is that the use of multiple clock domains introduces the problems of verifying asynchronous circuits in a design methodology based primarily on the abstraction of synchronous design.

At each clock domain crossing – when data moves from a flip-flop controlled by a clock in one domain to a flip-flop controlled by another – there is the potential for error. The main problems are metastability, data loss or unwanted changes in data value. A summary of typical avoidance techniques is given by Rich Faris in this article.