Steve Cline |  July 25, 2014
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
Rebecca Lipon |  July 20, 2014
The argument for an integrated approach to SoC verification
Pranav Ashar |  July 3, 2014
How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
Mick Posner |  May 24, 2014
ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
Bill Neifert |  May 15, 2014
While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging
John Ferguson |  April 28, 2014
The encryption chain for today's highly collaborative designs needs to be managed with care.
Pranav Ashar |  April 16, 2014
Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
Randall Myers |  April 8, 2014
Fighter pilots have long trusted highly sophisticated automation. That’s how you can meet the challenges posed by advanced PCB design techniques.
Joe Kwan |  April 3, 2014
Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
Julian Coates |  March 27, 2014
Shifting DFM validation earlier in the flow speeds NPI, cuts respins and gives you a critical edge.