Expert Insights

Chris Tice  |  March 17, 2014

The rise of hardware-assisted verification

Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.
Topics: EDA - Verification  |  Tags: ,   |  Organizations:   |  
Richard Goering  |  March 6, 2014

Henny Youngman’s advice to PCB designers

In a standing-room-only talk at the recent DesignCon conference, Eric Bogatin explained why comedian Henny Youngman could help them with signal integrity on PCBs.
Topics: PCB - Design Integrity  |  Tags: , ,   |  Organizations:   |  
Warren Stapleton  |  February 27, 2014

Next wave of innovation in verification technology must come from integration

The next boost to verification productivity will come from the integration of multiple strategies and tools.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  
Lisa Piper  |  February 26, 2014

Complexity drives smart reporting

Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.
Mark Bollar  |  February 11, 2014

The new landscape of advanced design

Advanced tools are being applied to established nodes to produce advanced designs for volume markets.
Sudhakar Jilla  |  February 6, 2014

Concurrency tackles MCMM issues head-on

The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.
Topics: EDA - IC Implementation, Verification  |  Tags: ,   |  Organizations:   |  
Colin Walls  |  January 30, 2014

Power management in embedded systems – new thinking required

Effective low-power design for embedded-systems will take a new culture of close collaboration between hardware and software engineers.
Mark Bollar  |  January 28, 2014

Are advanced designs only possible at emerging process nodes?

Advanced design isn’t restricted to emerging process nodes any more. Designers are using the latest tools to produce advanced designs on established nodes.
Jean-Marie Brunet  |  January 20, 2014

Patterning choices loom for 10nm and beyond

It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
Steffen Schulze  |  January 13, 2014

Consider your options for future nodes

If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.

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