Neil Songcuan |  January 7, 2014
The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
Mick Posner |  December 16, 2013
Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.
Carey Robertson |  December 9, 2013
Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
David Fried |  December 3, 2013
The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.
Brian Fuller |  November 11, 2013
In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
Jack Erickson |  November 1, 2013
Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
Richard Goering |  October 27, 2013
Forty six companies have joined the consortium developing the increasingly important IPC-2581 data transfer standard for PCB designs.
Piyush Sancheti |  October 16, 2013
Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Axel Scherer |  October 11, 2013
Verify registers without writing code for specific bus interfaces or speed up the loading of configuration registers using the UVM Register Layer. Videos show you how.
Adnan Hamid |  October 7, 2013
Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.