SiP promises advances in transmission speeds, bandwidth, accuracy and low power but verification requires careful evolution of existing tools.
How Calibre is evolving to address the challenges of LVS verification in early-stage design.
Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
A look at ways to improve LVS debug productivity on complex SoCs through more narrowly targeted debug strategies.
In sessions at the 2015 Design Automation Conference, engineers who had worked on finFET-oriented projects revealed how the technology has changed their design practices and where others may want to think twice about making the move.
A greater proportion of the layout requires more precise extraction at the 32nm and 28nm process nodes, so rules-based extraction tools can no longer deliver the accuracy needed to confirm acceptable electrical performance. Given the nature of parasitic elements in analog and mixed-signal (AMS) system-on-chip designs, designers need a parasitic extraction tool that provides gate-level, [...]
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