VHDL users also deserve efficient design and verification
More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.
FPGA
High-level synthesis for AI: Part One
The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
How virtual prototyping enabled Altera’s SoC FPGAs
The technique drove ‘agile systems development’ for the programmable logic vendor’s new product line.
Vivado HLS/AutoESL: Agilent packet engine case study
How Xilinx' Vivado HLS enabled the creation of an in-fabric, processor-free UDP network packet engine
Vivado, inside the new Xilinx design suite
The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
Improving ASIC prototyping on multiple FPGAs through better partitioning
Using a new design-partitioning tool and stacked-silicon interconnect FPGA to develop an ASIC prototyping platform that can be reprogrammed several times a day.
Strategic considerations for emerging SoC FPGAs
This white paper describes the emergence of SoC FPGAs, the drivers behind their market, and proposes some strategic considerations for executive management and system designers when choosing these devices.
Achieving teraflops performance with 28nm FPGAs
FPGA-based signal processing has traditionally been implemented using fixed-point operations, but high-performance floating-point signal processing can now be implemented. This paper describes how floating-point technology for FPGAs can deliver processing rates of one tril- lion floating-point operations per second (teraflops) on a single die.
Device native debug and verification for FPGA
GateRocket's RocketDrive facilitates integration of an FPGA into an HDL simulator to provide a "native" execution of a design on its target FPGA device. The companion RocketVision tool provides software-debugging capabilities that directly identify and enable the rapid resolution of bugs. This article considers the use of these tools in a "device native" verification and [...]
Ensuring reliability through design separation
System designs have traditionally achieved reliability through redundancy, even though this inevitably increases component count, logic size, system power and cost. The article describes the design separation feature in Altera software that seeks to address these as well as today’s conflicting needs for low power, small size and high functionality while maintaining high reliability and […]