ATPG

February 29, 2024

The keys to ensuring IC quality

How the latest DFT techniques pave the way for quality and success for today's advanced designs.
Article  |  Topics: EDA - DFT  |  Tags: , , , , , , ,   |  Organizations: ,
February 8, 2024
Ron Press is Sr. Director of Technology Enablement for Tessent at Siemens EDA. As a 30-year veteran of the test and DFT industry, Ron has presented seminars on DFT and test throughout the world. He is a member of the International Test Conference (ITC) Steering Committee. a Golden Core member of the IEEE Computer Society and a Senior Member of IEEE. Ron has patents on reduced-pin-count testing, glitch-free clock switching and on 3D DFT.

How AI improves DFT, test and yield

Take a high level view of the AI strategies used within the Tessent family to improve across-the-board performance.
August 27, 2020
total critical area feature - headline image

How to optimize test patterns based on critical area

The world of ATPG just changed with the introduction of a new way to create and choose the most effective test patterns.
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations: ,
July 9, 2018
Channel sharing and hierarchical DFT - Featured Image

Slash test time by combining hierarchical DFT and channel sharing

A hierarchical methodology removes DFT from the critical path for large designs. The methodology is compatible with other techniques such as channel sharing, which can further reduce ATPG turn-around time and test cost.
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations:
September 21, 2017

Yield is money – and other truths of diagnosis-driven yield analysis

Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
January 10, 2017
Silicon bring-up Tessent

Accelerate silicon bring-up in a bench-top environment

How a new software-led flow speeds silicon bring-up within the Tessent environment, including a Cypress Semiconductor case study.
Article  |  Topics: EDA - DFT, - EDA Topics  |  Tags: , ,   |  Organizations: ,
November 5, 2012
20nm test feature image

20nm test demands new design-for-test and diagnostic strategies

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations: , ,
August 18, 2012

When good DFT goes bad: debugging broken scan chains

Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations:
January 24, 2012

Design for test: a chip-level problem

The inherent complexity of today’s system-on-chips, with their multiple clock and voltage domains, requires test considerations to be moved further up design flows. The article describes strategies for and benefits from apply test before RTL goes through synthesis, augmenting what is already achieved through memory built-in self test and automatic test pattern generation.
Article  |  Topics: EDA - DFT  |  Tags: , , , ,

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