Mentor’s Dennis Brophy, Cadence’s Stan Krolikoski and Synopsys’ Yatin Trivedi describe how you can prepare to adopt Accellera’s Universal Verification Methodology.
In February 2011, Accellera approved and released the Universal Verification Methodology (UVM) standard along with an accompanying open source reference implementation and UVM User Guide. While their developers spend years crafting high-quality standards and understand them well, many possible adopters wait patiently until the standard is completed rather than track its development. In the case of UVM, a large class of potential users has also continued to use in-house methods while waiting on its arrival.
Now that the standard is completed, it is time to plan for deployment. At the 2011 Design Automation Conference, a half-day workshop was held to share details of UVM with a wider audience. Feedback suggested that the information was more ‘expert-level’ than something that would help a new adopter gain knowledge.
This article aims to help those who may not have tracked UVM’s development but, now that a standard is ready, want to get ready to deploy and then use it. We discuss how UVM came to be, what Accellera did to develop it and what educational resources are available from Accellera so users can plan their adoption.
UVM is based on work from the Accellera Verification Intellectual Property (IP) technical subcommittee (VIP-TSC). It was charged with two goals. The first was to develop a scheme by which two methodologies would allow verification IP (VIP) to interoperate if written for those different methodologies. The second and subsequent goal was to develop a ‘universal’ verification methodology that would pull from the known methodologies to represent a ‘standard’ methodology that would allow tool developers and design and verification teams to focus on one approach representing the state of the art with broad industry support.
The VIP-TSC anchored its standard on work rooted in the IEEE Std. 1800 (SystemVerilog) design and verification language. This includes the Verilog language for design that has extensions to support verification. Those who know SystemVerilog (SV) well might argue that it alone is a sufficiently complete representation of the needs of the verification community. While it is true SV code is portable on its own right in a design flow, the differing ways in which it is used make it hard to share verification schemes or methods across design teams or between companies that are attempting to collaborate on large, multi-team designs.
The Accellera UVM standard is built on top of a SV foundation (Figure 1). There are many published books on the SystemVerilog language that can be valuable resources. The SystemVerilog Language Reference Manual is available from the IEEE and another good resource.
UVM builds on a SystemVerilog foundation. Source: Accellera
In the days before SV, users had to create complex test cases manually or rely on proprietary technology that was not standards-based. In the early 2000s constrained random verification constructs were added to SV that allowed the verification engineer to automate the task of covering the verification space and move beyond manual directed tests. As the verification workload has grown with each silicon process node, the pressure to automate these tasks has gotten bigger and bigger.
As the industry adopted SV, different groups started to build verification IP (VIP) and environments but found that they did not interoperate or work well with each other. This led to an additional effort to allow VIP to work in a number of environments and the creation of bridging methods that allowed different environments to be pieced together. While verification teams may all have been speaking SystemVerilog, they were speaking in entirely differently terms. The release of UVM has brought a consistent meaning to those terms and opened the market to use a standard methodology to construct a testbench to improve interoperability and verification data portability.
A UVM testbench is composed of reusable verification environments called verification components. A verification component is an encapsulated, ready-to-use, configurable verification environment for an interface protocol, a design submodule, or a full system. Each verification component follows a consistent architecture and consists of a complete set of elements for stimulating, checking and collecting coverage information for a specific protocol or design. The verification component is applied to the device under test (DUT) to verify the implementation of the protocol or design architecture.
Figure 2 shows an example of a verification environment with three interface verification components. These components might be stored in a company repository and reused for multiple environments. The interface verification component is instantiated and configured for a desired operational mode. The verification environment also contains a multichannel sequence mechanism (i.e., virtual sequencer) that synchronizes the timing and the data between the different interfaces and allows fine-grain control of the test environment for a particular test.
Environment with three interface verification components. Source: Accellera
UVM provides the best framework to achieve automated verification coverage. It combines automatic test generation, self-checking testbenches and coverage metrics to significantly reduce the time spent verifying a design by:
- eliminating the effort and time spent creating hundreds of tests;
- ensuring thorough verification using up-front goal setting; and
- delivering early error notifications and deploying run-time checking and error analysis to simplify debugging.
This verification flow is different from traditional directed-testing flows. With UVM, you can start by setting verification goals using an organized planning process. You then create a smart testbench that generates legal stimuli and sends it to the DUT. Coverage monitors are added to the environment to measure progress and identify non-exercised functionality. Checkers are added to identify undesired DUT behavior. Simulation runs are launched after both the coverage model and testbench have been implemented. Verification of a working block, subsystem or system can then be achieved.
UVM allows you to thoroughly verify your design by changing testbench parameters or changing the randomization seed. Test constraints can be added on top of the smart infrastructure to tune the simulation to meet verification goals sooner. UVM promotes ranking technology development and solutions that allow you to identify the tests and seeds that contribute to the verification goals, and to remove redundant tests from a test-suite regression that do not contribute to the verification goals. UVM supports both directed and constrained-random testing. However, the preferred approach is for constrained-random testing to do most of the work before devoting effort to writing time-consuming, deterministic tests for specific scenarios that are too difficult to reach randomly.
Significant efficiency and visibility into the verification process can be achieved by proper planning. Creating an executable plan with concrete metrics means you can accurately measure progress and thoroughness across a design and verification project. By using this method, sources of coverage can be planned, observed, ranked and reported at the feature level. Using an abstracted, feature-based approach (and not relying on implementation details) helps you get a more readable, scalable and reusable verification plan.
With UVM, it is easier to know when you are done with verification or if you still need to do more.
What steps should those who want to learn more about UVM take to become proficient?
If you do not already know SystemVerilog, it would be important to have a good reference handy. This could include the IEEE Std. 1800-2009 standard or any of a number of books that cover SV for verification. The standard is available for download at http://standards.ieee.org/findstds/standard/1800-2009.html
With an understanding of SV in place, the next step is to build your proficiency in UVM. The Accellera UVM standard is defined by the UVM 1.1 Class Reference manual, the UVM 1.1 class library code reference implementation, and has an accompanying UVM 1.1 User Guide. These can be downloaded fee-free from the Verification IP (UVM) Accellera website at www.accellera.org/downloads/standards/uvm.
The UVM 1.1 Class Reference standard contains the definition of the UVM Class Library shown in Figure 3. It provides all the building blocks you need to quickly develop well-constructed, reusable, verification components and test environments.
The library consists of base classes, utilities and macros. Components may be encapsulated and instantiated hierarchically and are controlled through an extendable set of phases to initialize, run and complete each test. These phases are defined in the base class library but can be extended to meet specific project needs.
The library also provides various utilities to simplify the development and use of verification environments. These utilities support debug by providing a user-controllable messaging utility. They support development by providing a standard communication infrastructure between verification components using transaction-level modeling (TLM) and flexible verification environment construction using the UVM factory. The factory is a classic software design pattern that is used to create generic code, deferring to run time the exact specification of the object that will be created.
The UVM Class Library also provides global messaging facilities that can be used for failure reporting and general reporting purposes. Both messages and reporting are important aspects of ease of use.
To go deeper into UVM, Accellera suggests you explore its website and connect with the UVM community at Accellera’s UVM World (www.uvmworld.org). It contains a forum where experts and novices meet to share experiences to promote adoption and use of UVM and much more. Accellera maintains an ecosystem listing companies that offer a broad selection of tools, VIP, training and other consulting services.
Accellera has completed the standard. Now it is time for industry to plan its adoption—to ‘get ready’ and ‘set’ to deploy UVM.
Dennis Brophy is director of Strategic Business Development at Mentor Graphics. Stan Krolikoski is group director IP/EDA Standards & Alliances at Cadence Design Systems. Yatin Trivedi is director, Standards at Synopsys.