Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
Correlating production test failure diagnosis with DFM analysis can help identify and understand systematic yield issues, and to find out whether they are linked to DFM violations.
Richard Pugh reflects on efforts to cut through the tangle of cables and make emulation easier.
Open-source toolchains give companies ultimate control over their development environments, but how many can really afford the resources to debug and develop their own tools? Would they be better off with a commercially supported open-source approach?
The article describes a novel optimization approach that extends leading methodologies to improve performance, power and area. It is based on a pre-generated cell library that extends commercially available foundry libraries and couples it with novel logic optimization to aim for the delivery of near full-custom performance levels. The approach assesses the gate-level netlist generated [...]
We report from National Instruments’ annual user conference, NIWeek 2011, held in a sizzling Austin last month.
Mentor’s Dennis Brophy, Cadence’s Stan Krolikoski and Synopsys’ Yatin Trivedi describe how you can prepare to adopt Accellera’s Universal Verification Methodology.
The description of the stimulus to a device-under-test is becoming ever more complex. Complex constraint relationships need to be defined, and the use of randomly generated stimulus to achieve comprehensive coverage metrics is proving less predictable and more labor-intensive. Using the combination of a graph-based stimulus description with a more intelligent algebraic constraint solver, a [...]
We talked to Mentor Graphics CEO Wally Rhines about the solutions that already exist to combat increasing design complexity.
The article offers a case study of the DFM planning and methodology applied during a shrink of Cambridge Silicon Radio's UF6000 system-on-chip from the 130nm to 65nm.
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