EDA

November 5, 2012
20nm test feature image

20nm test demands new design-for-test and diagnostic strategies

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations: , ,
October 30, 2012
Mixed-Signal Methodology Guide

Verifying low-power intent in mixed-signal design

An exclusive extract from Cadence Design Systems' Mixed-Signal Methodology Guide provides an excellent overview of its discrete topic and a flavor of the book as a whole.
Article  |  Topics: EDA Topics, EDA - Verification  |  Tags: , , ,   |  Organizations: ,
October 26, 2012

Emulation delivers system-level power verification

Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.
Article  |  Topics: EDA Topics, EDA - ESL, Verification  |  Tags: , , , ,   |  Organizations:
October 23, 2012
A same net sliver

Better PCB design using the fabricator’s view

Early use of design for manufacturing can capture PCB yield issues related to pads, copper distribution, same net slivers and more
October 11, 2012
Tong Gao

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm, writes Tong Gao of Synopsys.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , ,   |  Organizations:
October 9, 2012

Physical verification of 20nm designs through integrated double-patterning analysis and repair

Finding and fixing double patterning problems in 20nm designs
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , ,   |  Organizations:
September 14, 2012

Moving to advanced reliability verification

Shrinking process nodes, rising power efficiency goals and burgeoning device functionality are stretching existing DFR techniques to their limits. This scalable methodology looks to address the shortfall.
Article  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations: ,
September 12, 2012

Critical tools for 20nm design

A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
September 6, 2012
Antun Domic

Getting ready for 20nm

Antun Domic of Synopsys tackles the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , ,   |  Organizations:
August 23, 2012
Pranav Ashar

Verification challenges require surgical precision

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:

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