EDA
Addressing SoC performance challenges in advanced deep-submicron CMOS processes
The white heat of technology
The Universal Verification Methodology: ready, set, deploy
Combining algebraic constraints with graph-based intelligent testbench automation
A matter of timing
Using DFM for competitive advantage
No double-quick growth for DDR3
Lane Mason Marc Greenberg DDR3 DRAMs still languish around the edges of the market despite their supposed attraction in terms of power and performance, the widespread availability of product, and the presence of a supposedly ‘evolved’ ecosystem and implementation infrastructure. Just over 18 months ago, Intel launched a major Go To DDR3 market initiative at […]
Bridging the ECAD-MCAD gap
New tools and standards encourage communication between the electrical and mechanical domains, says Pawel Chadzynski. Most major electronics companies have separate electrical (ECAD) and mechanical (MCAD) design organizations. Efficient collaboration between these teams throughout the PCB design process can significantly reduce cycle times, lower the risk of re-spins, and improve quality. The first challenge to […]
Inside the hot zone
Floorplanning informed by thermal analysis can significantly improve PCB layouts, writes Robin Bornoff The number of PCB design constraints seems ever increasing. The risk that a design will fail either functional performance or reliability goals grows for each generation. One increasingly popular trade-off addresses a balance between thermal compliance and signal integrity. Components with high […]
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