EDA

April 18, 2013
Network cables going into switch

Coding standards for secure embedded systems

Embedded systems are increasingly coming under attack as they hook up to the internet. Coding standards have emerged that make it easier to build code that is secure from the bottom up.
Article  |  Topics: Embedded - Architecture & Design  |  Tags: , ,   |  Organizations:
April 17, 2013
Xilinx 3D-IC interposer featured image

3D-IC integration – a stepwise approach

2.5D-IC integration overcomes 2D limitations such as cost, offchip bandwidth bottlenecks and I/O pin scarcity, and offers a route to true 3D-IC integration.
Article  |  Topics: EDA - IC Implementation  |  Tags: , ,   |  Organizations:
April 10, 2013
Marco Casale-Rossi is a senior staff product marketing manager in the Design Group at Synopsys.

Time to take up the 3D integration challenge

It’s time to take up the challenge of applying 3D integration technology to IC design. The manufacturing process technology is maturing, the tool chains are in place, and the opportunities to broaden your market by applying a new form of systemic integration are growing.
Expert Insight  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , ,   |  Organizations:
April 10, 2013
Richard Goering, senior manager of technical communications, Cadence

Focus on product creation for effective design

An increasingly important concept in design is that of product creation. An approach based on product creation looks beyond chip or board design.
April 9, 2013

How AMD implemented efficient clock gating analysis for Jaguar

The chipmaker used Calypto’s PowerPro to carry out power analysis of its latest core design at the RTL rather than at post-gate synthesis.
Article  |  Topics: EDA Topics, EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , ,
April 4, 2013
Michael Sanie, Synopsys

Debugging the debug challenge

Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
April 1, 2013

Improving SoC productivity through automatic design rule waiver processing for legacy IP

You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
Article  |  Topics: IP - Assembly & Integration, EDA - DFM, Verification  |  Tags: , , ,   |  Organizations: ,
March 11, 2013
Metastability at clock boundary

Clock-domain and reset verification in the low-power design era

The multiple clock domains on today's SoCs create a hotbed for clock-domain crossing bugs to thrive. Low-power design techniques increase the complexity of tracking these bugs down. Find out how these failures arise and what to do about them.
Article  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
February 12, 2013
Nithya Ruff, Director of Product Marketing for Virtual Prototyping Solutions at Synopsys.

Dev kits bring virtual prototyping to everyone

Now companies in any tier can use development kits as a platform to speed development, bridge the hardware-software divide and build out ecosystems quickly.
Expert Insight  |  Topics: Embedded - Architecture & Design  |  Tags: ,   |  Organizations:
February 12, 2013

How virtual prototyping enabled Altera’s SoC FPGAs

The technique drove ‘agile systems development’ for the programmable logic vendor’s new product line.
Article  |  Topics: Embedded - Architecture & Design, - Embedded Topics  |  Tags: , ,   |  Organizations: ,

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