RISC-V in nearly a quarter of designs (Wilson Functional Verification 2020 – Part One)
Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.
Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.
Accellera Systems Initiative has published for open review version 2.0 of the Portable Test and Stimulus standard.
This year’s IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
Mentor is packaging a range of software IP, reference designs, and technical help as VCO2S, for Vehicle Cockpit Consolidation Solutions.
Mentor’s latest additions to Tessent aim to cut test time by a factor of four but remains tailored for increasing design complexity.
A partnership between Siemens and VSI, a real-world autonomous vehicle research company, aims to refine and promote digital twin strategies.
The Arm Cortex-A78C extends the reach of the core into larger tablets and brings in one of a series of memory-protections extensions that will be used in the company’s standard cores.
The free-to-attend user meetings for Mentor clients will retain the same format mixing technical presentations with keynotes and networking.
Speakers at this year’s DVCon Europe called on the hardware community to find inspiration in software-development trends.
A Japanese component supplier is making it easier for its customers to choose the right parts for their designs by offering a powerful analog and mixed-signal (AMS) simulation environment through its website.