What hardware verification can learn from software development
What hardware designers can learn from software verification techniques such as agile, behaviour-driven development, code coverage and zero known defect strategies
EDA Topics
Back to basics – doing formal the right way
Considering design style, assertions, engines and coverage can help ease the development of an effective formal verification test plan
Applying agile techniques to IC design
How agile methodologies can be applied to personal and team practice in IC design, including for developing cloud accelerators at Microsoft
Verifying MIPI interfaces in SoCs
Verifying MIPI interfaces including CSI-2, CPHY, DPHY, MPY, Unipro and the UFS host controller on complex SoCs - should you make or buy the necessary VIP?
Eight tips for choosing your next FPGA tool
Eight issues to consider when choosing an FPGA tool, including risk minimisation, routing issues, ability to iterate, IP freedom and more
Technology trends demand netlist-level CDC verification
Complex processes and aggressive synthesis interventions are increasing the risks of metastability, creating a need for netlist-level CDC verification
Smaller designs face greater risk of respins
Research study suggests the maturity of your verification flow determines the likelihood of first-pass success far more than the complexity inherent in design size.
Verifying clock domain crossings when using fast-to-slow clocks
A look at three techniques to verify the validity of signals moving between clock domains
Fixing late ECOs in ARM core subsystems at STMicroelectronics
Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
Achieving safety and security in SoC development
Designers will have to update development processes to achieve the rigorous safety certifications required in automotive, rail, avionics and similar markets