verification

September 18, 2013

A common methodology to manage X propagation in both design and verification

How all types of engineer can focus on X states that represent real risk, and set aside those that are artifacts of a design process.
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February 5, 2013

Using VIP for cache coherency hardware implementations

Cache coherency implemented in hardware increases the verification effort. VIP-based strategies are described with particular reference to ARM protocols.
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January 31, 2013
Balance image for Cadence AVIP article

Accelerated VIP solves firmware and driver integration and validation tradeoffs

Trying to balance your use of simulation and FPGA prototyping is tough. Acceleration used with Accelerated VIP offers simulation-like visibility and debug with near FPGA performance.
January 24, 2013
Neill Mullinger, group marketing manager for VIP, Synopsys

Verification IP: the questions you should ask

How should you quiz your verification IP vendor to get the right VIP for your needs? Synopsys' Neill Mullinger details a checklist of the key points to raise.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:
July 26, 2012

Synthesizing assertions into hardware for faster silicon debug

Assertions are already used in pre-silicon verification and can help halve debug time. So why not synthesize assertions into real logic gates in the final silicon, to catch those unexpected bugs that make validation so much harder? Here’s how.
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May 28, 2012

Emulation

The value of the emulation market has almost doubled in the last four years as the technique becomes increasingly valuable to hardware/software co-verification.
May 21, 2012

Where there’s a will… there’s a way to better VHDL verification

An overview of the Open Source VHDL Verification Methodology and two of the libraries it uses.
April 5, 2012

Assertion-based verification

More than half of design companies claim to use ABV but many have yet to deploy full methodologies.
January 16, 2012

Unified Power Format (UPF)

The IEEE Unified Power Format (UPF) standard is intended to support low-power designs that use switchable power states and power islands.
June 2, 2011

Efficient RC power grid verification using node elimination

To ensure the robustness of an integrated circuit, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has been done to develop Model Order [...]
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