How all types of engineer can focus on X states that represent real risk, and set aside those that are artifacts of a design process.
Cache coherency implemented in hardware increases the verification effort. VIP-based strategies are described with particular reference to ARM protocols.
Trying to balance your use of simulation and FPGA prototyping is tough. Acceleration used with Accelerated VIP offers simulation-like visibility and debug with near FPGA performance.
How should you quiz your verification IP vendor to get the right VIP for your needs? Synopsys' Neill Mullinger details a checklist of the key points to raise.
Assertions are already used in pre-silicon verification and can help halve debug time. So why not synthesize assertions into real logic gates in the final silicon, to catch those unexpected bugs that make validation so much harder? Here’s how.
The value of the emulation market has almost doubled in the last four years as the technique becomes increasingly valuable to hardware/software co-verification.
An overview of the Open Source VHDL Verification Methodology and two of the libraries it uses.
More than half of design companies claim to use ABV but many have yet to deploy full methodologies.
The IEEE Unified Power Format (UPF) standard is intended to support low-power designs that use switchable power states and power islands.
To ensure the robustness of an integrated circuit, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has been done to develop Model Order [...]
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