Executable specifications boost SoC and IP efficiency
Automating executable specifications as they evolve can deliver major efficiencies.
SoC
Enabling embedded multicore systems with multiple OSes and critical goals
Embedded multicore systems require engineers to make choices around the hardware and software architectures, approaches to certification and more. This is a guide to the trade-offs involved and how to best leverage your options.
Doc Formal: Achieving exhaustive formal verification of packet-based designs
Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.
How hardware emulation helps drones take flight
In an exclusive interview, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs with Bo Shen, founder of fabless specialist Artosyn.
Taking risk out of software-driven networking SoCs
How virtualization and integration with hardware testers are enabling networking SoCs in the billion-gate era.
Enabling FPGA prototyping of large ASIC and SoC designs
How tool parallelism, automatic partitioning, deep debug memories and time domain multiplexing eases FPGA prototyping of large ASIC and SoC designs
It’s time to embrace objective-driven verification
How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
Using HAPS to streamline IP to SoC integration
The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
Think like designers to fill the SoC verification gap
Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.
Knock down the wall to SoC integration
SoC integration can be accelerated by using virtualization to make the benefits of emulation more accessible to both hardware and software engineers.
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