What is FD-SOI and why is it useful?

Fully depleted silicon-on-insulator (FD-SOI), also known as ultra-thin or extremely thin silicon-on-insulator (ET-SOI), is an alternative to bulk silicon as a substrate for building CMOS devices. SOI wafers have a shallow layer of epitaxial silicon grown on top of an oxide layer that acts as an insulator. The top silicon layer is fully depleted, that is, it doesn’t have any intrinsic charge carriers, which has a number of advantages when building deep submicron devices.

Transistors built on FD-SOI have a very thin (shallow) channel, which improves the gate’s ability to remove carriers from that channel when the device needs to be switched Off. In principle, FD-SOI offers better performance than conventional bulk silicon on deep submicron process technologies, with particular benefits for low-power circuits. Proponents of FD-SOI argue that, although the resultant devices’ current drive is poorer than in bulk processes, the drain-induced barrier lowering (DIBL) that plagues deep submicron processes by making it more difficult to turn devices fully off is greatly reduced by the presence of the insulating oxide layer directly beneath the channel.

According to the SOI Industry Consortium, benchmarks show that using FD-SOI makes it possible to reduce the operating voltage in SRAM cells by 100-150mV. Cutting the voltage in regular CMOS has proved difficult because of concerns over variability, as it slashes the static noise margin and so increases the probability of errors in the memory array. The Consortium claims that the operating-voltage reduction afforded by FD-SOI enables a 40 per cent reduction in memory-array power consumption.

Another potential advantage of FD-SOI over the finFET, its nearest competitor for sub-28nm processes, is that the approach makes it possible to back-bias the channel and so gain greater control over the charge carriers flowing through it.

What effect does FD-SOI have on design?

The use of a very thin channel deals with one of the main design problems of previous, partially depleted SOI implementations that used thicker silicon channels. This is the tendency for electrical charge to remain under the gate once a transistor has been turned Off. This ‘history effect’ complicates design because circuits need to take account of the possible changes in voltage that the effect causes. FD-SOI transistors do not, in general, exhibit this behavior.

In principle, it is possible to directly port a cell library from a bulk process on to an FD-SOI process. However, the results will not be as good as dedicated cell libraries designed to take advantage of the different balance of capacitances in FD-SOI devices and the reduced variability of undoped channels, which should improve static noise margin in SRAMs. Subthreshold leakage should be greatly reduced with FD-SOI and the SOI Consortium claims that criteria important to analog design, such as transconductance, also benefit from undoped channels.

The SOI Consortium has proposed that a ‘safe’ way to adopt FD-SOI is to start by using hybrid FD-SOI/bulk co-integration. In this approach, IP cores that are deemed too risky to redesign are placed on to areas of the wafer that expose the bulk silicon, while synthesized logic optimized to use FD-SOI structures and design rules is placed on to areas of the wafer that expose FD-SOI.

The biggest impact on design will come from a proposed advantage of FD-SOI: the ability to dynamically back-bias the channel, which gives better control and so improves device switching speed. One advantage of using back-bias in FD-SOI is that its effect does not diminish with decreasing device size in the way that it does for bulk silicon.

Multi-Vt circuitry is more complicated to implement on FD-SOI than with bulk silicon processes because channel doping cannot be used to alter the threshold voltage. Instead, the threshold voltage is controlled by tuning the gate stack materials. However, a combination of doping and active biasing can be used to alter the threshold of a target group of transistors that have a common, sub-oxide backplane. The contacts and implant regions for these groups have to be defined at design time. However, the Vt rolloff is less pronounced in FD-SOI than with comparable bulk-silicon devices. GlobalFoundries said it would offer two Vt options: RVT and LVT.

Although multi-Vt support is more difficult, designers looking for low-power performance are more likely to use body-bias techniques, which FD-SOI supports more readily than bulk silicon. The combination of forward and reverse body bias makes it possible to dynamically adjust switching performance and leakage. Forward body bias improves switching speed at the expense of leakage. Reverse body bias is used to cut leakage for quiescent transistors. According to ST, FD-SOI provides much greater control over body bias than is possible in bulk. However, the designer has to select whether performance or leakage is more important for the transistors within a power island as the forward and reverse bias ranges depend on the doping of the well in which the transistor sits. Going beyond the bias range creates a parasitic diode between the n- and p-wells.

If optimized for forward body bias using the ‘flip well’ doping scheme, the effective gate voltage of the transistor can be boosted by as much as 3V, but this restricts the reverse bias shift to -300mV. Conversely, using the standard well configuration, reverse body bias can be extended to -3V, limiting forward bias to 300mV.

The advantage of the large reverse-bias form of FD-SOI is that it provides very low leakage without resorting to retention gates, which should result in blocks that can wake up very quickly after being put into a ‘drowsy’ mode by the biasing control logic. Blocks using the flip-well structure will tend to use retention cells and power gating for sleep control.

Further leakage control is available through what ST calls poly biasing, carried over from bulk processes With this, the channel length of the transistor is changed at the design stage similar to the technique used on bulk processes. A leakage recovery process analyzes the transistors used on each timing path and then uses cells with a longer transistor channel length for those that are not on critical paths, further reducing their leakage.

Synopsys has worked with ST on test chips designed to evaluate the power-performance tradeoffs of FD-SOI, such as an ARM Cortex-A57 and A53 devices that make extensive use of body-biasing techniques. Implemented using IC Compiler, the test chips demonstrated DVFS scaling over the range 0.5V to 1.4V, with operating frequency from less than 300MHz to 3GHz. ST engineer David Jacquet described the implementation in a presentation at ARM TechCon 2013.

One potential issue with designing for FD-SOI is that of self-heating, similar to that encountered with finFETs, because the ultra-thin narrow channel lies on top of a poor thermal conductor. However, this is not expected to affect low-power circuits, which remain the primary target for proponents of FD-SOI-based designs.

When and where can I use FD-SOI?

Fabless companies will be able to access the technology through foundries GlobalFoundries and Samsung Semiconductor. A deal between GlobalFoundries and STMicroelectronics was signed at the beginning of 2012 that covered the 28nm version and what was then the 20nm shrink of the technology. GlobalFoundries said it would buy suitable wafers from bonded-wafer specialist Soitec for 28nm FD-SOI mobile-phone devices and provide access to the technology from 2013. However, production does not appear to have started.

Samsung decided to sign its own deal with ST in May 2014, with plans to start production in early 2015. Following the deal, GlobalFoundries reiterated that it continued to work on FD-SOI but did not comment further on plans.

ST is able run its own devices either at its relatively small Crolles plant, where its FD-SOI process was developed.

What are the risks and downsides of FD-SOI?

The primary problems with FD-SOI lie in the supply chain. Although it is possible to create the oxide layers on bulk silicon wafers and then use epitaxy to define silicon channels on the surface, the surface quality needed for nanometer processes is best supported through the use of specialized, bonded SOI wafers. As with any non-mainstream process, these wafers are more expensive although some cost savings could be achieved through simpler processing at the transistor-building stage. For example, the channel does not need to be doped, which causes fewer problems with variability and, therefore, device yield.

A key issue with FD-SOI is one of long-term commitment. The initial high-volume project for FD-SOI at ST was for the ST-Ericsson NovaThor L8580 mobile-phone applications processor. Following the decision to split up ST-Ericsson and pass control of modem chipsets back to Ericsson, the FD-SOI version of the NovaThor was cancelled. The lack of an obvious high-volume user of the technology has led to concerns that ST may find it difficult to continue its own development effort. However, ST is not working alone as it partners closely with CEA-Leti on FD-SOI process development and the company has claimed to be working on multiple projects for customers. The company has an active involvement in ICs for networking infrastructure projects, supported by IP such as the intelligent memory controllers designed by Memoir Systems, which were ported to FD-SOI in 2013.

In terms of design risk, both CEA-Leti and ST claim it is relatively low. ST has developed its own foundation libraries that include embedded memories, test, and I/Os. As well as Memoir, ST has worked with partners to have IP ported to FD-SOI and those companies have reported the process to be relatively straightforward. Cadence has ported IP such as DDR controllers to FD-SOI and qualified physical design tools for the process.

CEA-Leti produced a compact model for SPICE that provides support for the wider bias ranges for FD-SOI that ST aims to exploit in December 2013, describing it at IEDM that year. A Verilog-A version is also available through CEA-Leti. UC Berkeley expects to release soon a standard compact model for FD-SOI that will scale to experimental materials systems such as molybdenum disulfide that can be used as single atomic-layer SOI systems.

The Leti-UTSOI version 2.0 compact model includes a full description of the creation of an inversion layer at the rear face of the silicon film, so it is able to describe transistor behaviors over a large polarization range applied both at the front and at the rear interface of the transistor.

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