Parting of the ways

Intel’s recent announcement of its decision to use finFETs for its 22nm process brought into sharp relief the need to re-examine the future role of planar transistors on bulk silicon wafers, and whether it has a role at all. 

During a session organized by the North California Chapter of the American Vacuum Society, Sematech’s CMOS scaling program manager Chris Hobbs explained the background to the need to consider a shift in device types: “Historically, people have made devices smaller to gain more performance.”

Classical scaling then started to fail to deliver performance gains on its own. Process designers began to incorporate greater amounts of strain and higher levels of doping.

Serge Biesemans, vice president of technology at IMEC, recalled in a session on future device architectures: “Strain used to be a negative thing. But from 2002, the call for greater levels of strain came in.”

The amount of strain needed for p-channel PETs has increased dramatically, said Hobbs. He showed how the orientation of the silicon crystal lattice influences the behavior of n- and p-channel devices. PFETs offer higher mobility when built on a (100) surface, with performance dropping off if the lattice is rotated to provide a (110) surface.

“For PFETs, it’s the other way round,” said Hobbs. “People have said, ‘We will take the (100) surface for its NFET performance and use strain for the PFETs.’”

Although process designers have gradually improved mobility and device performance, it has come at a cost. Increased channel doping has led to greater levels of variability as dimensions have reduced. 

And, as the drain and source have moved closer together, effects such as drain-induced barrier lowering and leakage have become far more prominent.

Hobbs said: “In planar devices, as the source and drain get closer together, the gate loses the ability to control the channel.”

Ali Khakifirooz, lead device engineer for extremely thin silicon-on-insulator (ETSOI) technology at IBM, said the gate length stopped scaling in the past couple of nodes. But this has led to the distance between the gate sidewalls and drain and source moving much closer together. There is now very little space left: “At 22nm we need to start scaling the gate length again.”

“We need to go to new types of devices, such as finFETs,” Hobbs said. “The nice thing about the finFET is its lower dependence on orientation for NFET performance.”

The mobility curves for NFETs on both (100) and (110) surfaces follow almost the same profile. It is a different story for PFETs, where the (110) surface prevails. Hobbs said this makes it possible to change strategies: “You can orient for p-channel performance and then use fewer dopants, so you get less scattering in the channel.”

Referring to Intel’s announcement, Biesemans said: “Finally the finFET is here. It is likely to be the mainstream device adopted by the major manufacturers. Intel’s announcement explains why finFETs can deliver. The finFET delivers a steeper subthreshold slope than equivalent planar devices: you can use that to reduce power or design it for improved circuit speed.”

For the same circuit speed, a finFET can run at a voltage that is 0.2V lower, delivering 50 percent lower active power consumption, Biesemans claimed. By effectively wrapping the gate around the fin-shaped channel, the gate is able to once again fully deplete the channel of carriers when the device needs to be switched off, greatly reducing leakage.

However, there are manufacturing challenges that may, in turn, affect circuit designers. The original finFET architecture called for the fins to be built on an SOI substrate. Later work showed that it is possible to build finFETs on cheaper bulk-silicon wafers, but that is more prone to variation.

“One thing that is different with fins is that with planar devices, lithography determines the electrical width. With the finFET, it’s the height that defines the electrical width,” said Hobbs. And the effective height depends strongly on the shallow trench isolation oxide that surrounds the fin itself. Variation in that will lead to subtle changes in behavior from device to device.

“A lot depends on how much variation you can tolerate, and how good your process control is,” said Hobbs.

However, Intel has been a strong proponent of chemical mechanical polishing (CMP), citing it as one of the key technologies behind the company’s choice of gate-last for its 45nm and subsequent high-k metal-gate processes. In a paper presented at the 2008 International Electron Device Meeting (IEDM), Intel’s Joseph Steigerwald described the ways in which the company employed CMP and cited it as an enabling technology for finFET construction.

Speaking at an event organized by CEA Leti, Olivier Faynot, an engineer at the French research institute, claimed there is a further problem for the finFET: “In practice, you have to use very aggressive finFET devices with very aggressive fin width.”

Biesemans explained: “If the fin is too wide you don’t really get the benefit of fully depleted channels.”

Faynot and Khakifirooz argued the ultra-thin body (UTB) or ETSOI architecture offers a better combination of features. This makes it possible to continue to use planar transistors, using SOI substrates with very extremely thin, undoped silicon to provide a fully depletable transistor channel. 

“We see the ETSOI as having a very good tradeoff,” Faynot claimed. “And 15nm devices have already been reported.”

Historically, ETSOI devices have suffered from comparatively poor drive strength. SOI advocates such as Thomas Skotnicki, director of advanced devices at STMicroelectronics, have typically worked closely with CEA Leti researchers. Skotnicki argues that the drive strength only matters for high-performance designs, such as PC processors. For low-power SoCs, parameters such as DIBL are more important.

Faynot and Khakifirooz pointed to recent results disclosed at this year’s VLSI Technology Symposium, which took place a few weeks ahead of Semicon West. These showed drive strength approaching that of other experimental 20nm-class processes. But that is not the key to ETSOI’s claim for use in processes of the future.

“One thing that is very important is back bias,” said Faynot. “Planar SOI provides the ability to control the Vt [threshold voltage] of the transistor with an additional transistor. Tuning the Vt of the transistor is not possible with finFETs. With ETSOI, you can modulate the drive strength and leakage through back bias.

“This effect directly translates into a tradeoff at the circuit level. By switching from bulk at 28nm to ETSOI at 20nm, you can obtain a 30 percent speed improvement. Or you can lower voltage by 0.2V, which translates into 50% power consumption reduction.”

The figures are broadly similar to those of Intel’s claims for finFETs. However, Faynot said the advantage of ETSOI is that the back bias control makes it possible to alter the properties of transistors across a wafer by mixing and matching different back bias voltages with the two different work-function metals that process designers will select for the core n- and p-channel transistors. Attributes such as threshold voltage can only be set on finFETs by altering the work function of the gate metal stack—and so can only be done during process definition.

“The work function difference for finFETs is smaller than on bulk, which makes it easier to select a dual work-function solution,” Biesemans claimed.

Of the two candidate device architectures facing designers today, Biesemans argued: “Both are viable options for a fully depleted channel. The question is whether one is more optimum for high performance or one for mobile. I think the jury is still out there.”

Biesemans said the crucial difference comes down to the circuit level: “One has three terminals and the other has four. The FinFET has lost the back bias terminal. But for high-performance parts you don’t really need it. However, if chip architectures require voltage islands and the ability to shut leakage off locally then that would be the perfect option. That for me is a deciding factor: drive strength or fully depleted. That is a choice up to the chip designer.”

Raj Jammy, vice president of materials and emerging technologies at Sematech, said: “There is also a commercial angle: how much will the supply chain nucleate around a specific option?”

Historically, the semiconductor business has favored just one dominant form of mainstream CMOS. But if the industry continues on parallel development with two different device architectures, Faynot said he expects they will ultimately come together: “FinFET and FD SOI will merge around the 11nm node. Then, at 8nm and below, nanowires will provide the perfect electrostatic control.”

By this time, Faynot said: “Materials such as III/V will be mandatory to increase drivability.”

Jammy said: “The good news is that we are not replacing silicon. Materials such as III/V and germanium will go on top of silicon because over time we need to look at reducing the operating voltage further. Once you have III/V or germanium with their higher carrier mobility, you can operate the device at a much lower voltage.”

The issue will be how to make reliable devices cost-effectively. Today’s designs rely on complex arrangements of buffer layers to avoid lattice defects, and many of the materials used in conventional III/V production such as gold are not compatible with silicon CMOS process, Jammy explained. However, there is more unity around the architecture of the transistor of 2020 than there is for the device of 2012 or 2014.

Chris Edwards is a freelance technology writer based in London.