EDA

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies

An exclusive extract from Cadence Design Systems' Mixed-Signal Methodology Guide provides an excellent overview of its discrete topic and a flavor of the book as a whole.

Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.

Early use of design for manufacturing can capture PCB yield issues related to pads, copper distribution, same net slivers and more

Manufacturability, routing, library design and more - it all needs rethinking at 20nm, writes Tong Gao of Synopsys.

Finding and fixing double patterning problems in 20nm designs

Shrinking process nodes, rising power efficiency goals and burgeoning device functionality are stretching existing DFR techniques to their limits. This scalable methodology looks to address the shortfall.

A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design

Antun Domic of Synopsys tackles the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.