Real Intent tool looks at paths to hardware vulnerability
Real Intent has developed a tool for identifying potential security issues in chip designs at the sign-off stage.
static analysis
A new methodology addresses the increasing challenge of reset domain crossing
Originally presented at DVCon Europe, a new paper automates complex steps in RDC verification and reduces noise.
A hardware-centric approach to checking HLS code before synthesis
Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
Real Intent updates lint tool, adds Matlab and Simulink support
More lint rules, better SystemVerilog support, links to MATLAB and Simulink