April 22, 2015

Fusion core targets voice-activated devices

Cadence has launched a processor core aimed at ‘always on’ signal-processing applications such as voice detection and recognition for wearables.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations:
May 29, 2014

Synopsys adds vector DSP operations to ARC EM processor IP

Synopsys has developed a digital signal processing (DSP) instruction set extension to its EM family and two cores that employ it.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
April 24, 2014

Altera finds a way to cheaper floating point in FPGAs

Altera has revealed that the DSP blocks in the Arria 10 FPGAs contain the logic needed to make them work as IEEE754-compliant floating-point units.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , ,   |  Organizations:
June 14, 2013

Synopsys launches single kit to optimize IP across PPA

Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
Article  |  Topics: Digital/analog implementation, Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,
October 12, 2012

OMG adopts portable image and signal processing libraries

The Object Management Group has adopted the Vector Signal and Image Processing Library (VSIPL) for C and VSIPL++ for C++ as standard specifications that it will manage and promote.
Article  |  Topics: Commentary, Blog - Embedded, - Standards  |  Tags: , , ,   |  Organizations:


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