Real Intent links tools to Synopsys flows through in-Sync program
Real Intent has linked its key tools into Synopsys’ VCS Verilog simulation and HDL Compiler tool flows.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
ANALYSIS: nVidia has the IP to license but what about the ecosystem?
To get others to adopt its GPU cores, Nvidia must quickly build partnerships with tool vendors and foundries that guarantee easy implementation.
nVidia to license GPU technology as IP cores
Graphics chipmaker nVidia has said it plans to license as IP cores some of its technology in the hope of building up a customer base among other chipmakers and systems houses developing their own SoCs.
Microsemi focuses on security with Igloo2 FPGAs
Design security is a major target for Microsemi’s update to its Igloo series of flash memory-based FPGAs, which add an ARM-oriented memory subsystem.
Real Intent highlights hierarchical clock domain crossing with Meridian 5.0
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Synopsys doubles speed of formal ECO checking
Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
Atmel bridges 8 and 32bit gap with ARM M0+ family
Atmel has launched its first family of microcontrollers based on ARM’s Cortex M0+ with features to ease PCB design and provide programmable serial ports.
Synopsys launches single kit to optimize IP across PPA
Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
Altera outlines process roadmap for ‘Gen 10’ FPGAs
Altera has disclosed a number of the features that will make it into the top end of its upcoming ‘Generation 10’ family of FPGAs.
FinFET shift could drive analog automation as layout effects bite
The arrival of the finFET brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.