Technical Newsletter #2: 14nm and Beyond, Low Power, Double Patterning, CPTF

By Chris Edwards |  1 Comment  |  Posted: March 8, 2012
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In this issue

  • Chris Edwards introduces our interviews with key speakers at next week’s Common Platform Technology Forum, and highlights our presence at Cadence’s CDN Live and Europe’s DATE conferences.
  • Dr Mukesh Khare of IBM Research discusses the ‘Innovation Pipeline’ beyond 14nm.
  • Kelvin Low of GlobalFoundries describes how fabless companies can exploit 28nm processes.
  • Michael White of Mentor Graphics dispels the fear, uncertainty and doubt over double patterning from 20nm.

Also, don’t forget to check out the latest technical postings on the main site at the end of the newsletter.


Welcome to our second newsletter. This time we feature more interviews with members of the Common Platform foundry alliance (GlobalFoundries, IBM and Samsung) ahead of the physical and virtual editions of its annual technical conference. The Common Platform Technology Forum 2012 takes place on March 14. The physical event is at the Santa Clara Convention Center. The Virtual Technology Forum takes place from 9am PT, also on March 14.

Registration is now open for both, and you can review the two complete programs via the same link. The virtual forum will be archived for access throughout 2012.

This newsletter focuses on three companies: Common Platform members IBM and GlobalFoundries, and one of the platform’s leading ecosystem partners, Mentor Graphics.

Meanwhile, these newsletters are a new concept for us, so we’re eager for your suggestions and feedback on the format as well as any topics we have covered or should cover. The same goes for the website. Contact us at

And remember to visit the main Tech Design Forum website next week. It’s a busy one for electronics design with Cadence Design Systems’ user conference, CDN Live, also taking place in San Jose while DAC’s European sister, Design Automation and Test in Europe (better known as DATE), hosts its 2012 edition in Dresden, Germany. We’ll be reporting live on site from all three. My colleague Luke Collins and I will be in Dresden and hope to meet some of you there. The other member of the team, Paul Dempsey, will be following developments in the Valley.

Chris Edwards

More than pipe dreams

Dr Mukesh Khare, IBM Research

What does the landscape look like beyond 14nm? Dr Mukesh Khare of IBM Research is well placed to answer that.  He gave us an overview of the challenges in the ‘Innovation Pipeline’.

TDF: What major challenges do you see in moving beyond 14nm?

Mukesh Khare: The most immediate priority is leveraging finFET device structures to be a solution for more than one generation followed by innovating to deliver the ultimate device that can be built in silicon. Equally important, though, is pushing the limits of optical lithography while extreme ultraviolet (EUV) technology gets ready for primetime.

Have we identified technologies that could help us achieve those goals?

Several innovations in the pipeline will allow us to continue evolving device structures and achieve both higher performance and lower power. Some near-term options extend silicon technology; some longer-term ones target advanced materials. The technology pipeline has a special focus on improving mobility and reducing parasitics through innovative methods, such as multi-patterning to provide adequate technology scaling and an aggressive push on EUV.

It does seem likely that we’ll be looking at some new materials as well as structures and other techniques.

Our research team has made excellent progress looking at the ultimate silicon device structure, nanowire, and also at the use of alternative materials to improve mobility. At IBM, we have multiple proof points, including a demonstration of what are currently the highest performing carbon nanotube devices.

Are we likely to see changes that have a significant, maybe radical impact on design flows and practices?

A radical change is happening with the introduction of finFETs. The extended design community needs to familiarize itself with that to leverage the benefits of these 3D devices. As 3D device structures are enhanced in successive technology nodes, new design techniques will continue to be leveraged.

However, we have close collaboration with the EDA vendors in our ecosystem and together we provide approaches that minimize the effect of change on designers as much as is reasonably possible, while allowing them to fully leverage new capabilities of the technology.

Could any of these techniques relieve the rising costs of manufacturing?

Certainly, a breakthrough in EUV throughput could definitely benefit all of us. But our ongoing effort to continue driving scaling consistent with Moore’s Law reduces costs as well.

Dr Mukesh Khare will speak on The Innovation Pipeline Beyond 14nm Technology at the Common Platform Technology Forum 2012 on March 14. The session begins at 4pm in Great America 1/2/3 at the Santa Clara Convention Center. Click here to register.

Delivering tomorrow’s technology today

Kelvin Low, GlobalFoundries

How does mobile change the game? What about high-k, metal gate (HKMG)? And how do Common Platform members structure the process? Kelvin Low, Deputy Director, Product Marketing, Leading Edge Technologies at GlobalFoundries offered his insights.

TDF: Parameters such as drive strength traditionally controlled leading-edge process development. Are different process-level ones now taking precedence?

Kelvin Low: This is tied to leading-edge product introduction. There are high performance products – CPU, GPU, FGPA – that push performance limits whereby pure transistor drive currents drive the technology definitions. However, consumer products &#8212 especially for mobile &#8212 are also driving the need for leading edge technologies. There, the push for smaller devices and more functionality drives area scaling. All-day battery life drives lower power and standby currents, while hunger for more content drives the need for more processing power and hence performance. Development of leading edge processes today is definitely more challenging.

How do low power (LP) processes impact design? For example, do they require new sets of design rules?

Well, they don’t need different design rules. Our LP processes share the same set of rules as the high performance process. In fact, our 28nm LP process implementation using HKMG gate-first eliminates the need for complex stress engineering and thus reduces the number of restricted design rules. It also saves cost, crucial for consumer applications. This makes design implementation easier.

HKMG processes have opened up process options in terms of the balance between power consumption and performance. How can customers balance those?

HKMG has allowed technology scaling beyond 40nm &#8212 the electrostatics properties of the traditional gate dielectrics using oxide had reached their limit. It provides better short channel control while exhibiting low gate leakage properties versus a low power option using poly-sion gate dielectrics. The properties of HKMG in a differentiated gate-first implementation have allowed factors such as power, performance and area to also be optimized against design goals.

To do this, GlobalFoundries is providing both process technology support and design support. We have augmented our resources to help customers understand tradeoffs, especially at the leading edge. We have had multiple successes here where we have jointly realized the design goals of our lead adopters

How are you working with ecosystem partners to deliver tools and IP even while the process is evolving?

We work with our GlobalSolutions partners on many levels. We have long-term relationships with EDA and IP partners for design enablement across multiple nodes where we meet at the customer with silicon-proven design solutions intended to ensure the lowest risk for first-time-right SoCs. This includes early engagement with these partners to prove design flows, physical IP, optimized embedded cores, analog/mixed signal IPs, complex interface IPs, and more.

Partners also play a key role in early development. For example, we recently announced that we have taped out a 20nm test chip that includes an ARM Cortex dual-core A9. It required early library development with ARM as well as early router support from Synopsys. We have already initiated 20nm EDA and IP engagements with our partner ecosystem across the spectrum of design enablement solutions and continuously integrate their feedback into process development.

Kelvin Low will present a talk on Enabling Processors With Low Power Consumption in a Market Efficient Process at the Common Platform Technology Forum 2012. The session begins at 2:00pm on March 14 in Great America J at the Santa Clara Convention Center. Click here to register.

Double patterning without tears

Michael White, Mentor Graphics

Double patterning will arrive at 20nm. Michael White, Director of Product Marketing for Calibre Physical Verification Products at Mentor Graphics, detailed the background to this latest addition to the design arsenal and how to overcome the challenges it presents.

TDF: Why do we need double patterning?

Michael White: To counteract diffraction effects caused by using 193nm illumination to produce sub-28nm features. In double patterning, one mask’s features are split across two less densely patterned masks to improve the chances of creating the right features on the wafer.

Is double patterning a single-node solution, given the prospect of extreme ultraviolet (EUV) sources whose short wavelengths reduce diffraction effects?

Today, EUV looks like a Rolls Royce solution today, suitable for those who can optimize their process for one product like memory-makers. Foundries can’t offer that optimization to multiple customers. They need an approach &#8212 such as adding more masks to their standard processes &#8212 that is familiar to the ecosystem and works well for everyone. It remains to be seen whether mainstream foundry customers will need EUV at 14nm. Double or even multi-patterning techniques may still work.

How much impact will double patterning have on design and verification?

IP vendors make an interesting case study here. They have been worrying about issues such as critical area analysis since 65nm. As they move toward 28nm and 20nm, they are doing more work on the impact of litho printability and planarity issues. They have to make their IP as robust as possible because they’re never sure of the context in which it will be used. Analog IP designers want to control how their designs are split by double patterning, rather than relying on the foundry to do the splitting for them. So there is little new here, just greater complexity and a need for greater attention to detail.

How far up the design flow will double patterning go?

People talk about ‘restricted design rules’ for double-patterned designs, but I think of them as ‘realistic design rules’: “This is what we can do and we want you to know upfront.” With Calibre, we can go from IP to block to chip to hand-off using the same underlying algorithms, giving the designers a definition of the process via the Calibre design kits and software.

How will tools vendors help designers work within the constraints imposed by double patterning? Are there new features that will help designers address these impacts?

We introduced pattern-matching to our tools at 28nm, so designers could highlight an area of the design likely to cause printability issues and then have the tool search for similar instances. For 20nm, we’re offering a new way to manage the addition of dummy fill, which improves planarity. We’ve found that at 40nm analog designers need a wider choice of fill shapes, in both metal and poly layers, to counter the effects of rapid thermal annealing without affecting circuit performance. Digital designers are likely to need this level of control at 20nm as well.

Michael White will give a presentation on Double Patterning at 20nm: What is it? Why do I Care? And How to Leverage the Common Platform Solution at the Common Platform Technology Forum 2012 during both the physical and virtual events. His session at the Santa Clara Convention Center takes place at 3:00pm on March 14 in Great America K. His online presentation begins at 4:00pm PT, including live chat at the end of the main talk. Click here to register for either.

Now online

Tech Design Forum is changing. Read more.

PCB integration:
Envelope tracking for RF PAs in handset systems

Three essential steps to SoC design and verification

Advanced manufacturing:
IMEC readies finFETs for 14nm PDK

Design starts:
Gartner tracks continuing shift to ASSPs

Highlights at DATE 2012

Guest blog:
ISQED 2012 expands brief, adds colocated events

Issue #1: ARM on finFETs, Cadence on 20 and 14nm, Samsung on mobile

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