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state machine
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February 26, 2014
Complexity drives smart reporting
Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.
Expert Insight | Topics:
EDA - Verification
| Tags:
deadlock
,
error reporting
,
formal verification
,
FSM
,
state machine
,
unreachable code
| Organizations:
Real Intent
EDA Topics
DFM
DFT
ESL
IC Implementation
Verification
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