This two-part article describes the advantages achievable in deploying a hardware emulation platform in virtual mode that boosts the design verification productivity by an order of magnitude versus in-circuit-emulation (ICE) mode.
The first part of this series detailed the virtual mode and its advantages over traditional in-circuit emulation (ICE). This second part describes an implementation called Veloce VirtuaLAB that increases your return-on-investment (ROI) from an emulation platform used in virtual mode.
Currently, all hardware emulation suppliers support the virtual mode and capitalize on the benefits discussed in Part 1 of this two-part series.
The Mentor Veloce VirtualLAB technique arguably goes a step further. It encapsulates an entire virtual test environment that can be customized for specific applications as a replacement for an equivalent physical testbench.
Veloce VirtuaLAB replaces hardware models with accurate virtual peripherals, such as software models consisting of pre-validated IP that process target hardware protocols in software. The virtual setup is functionally equivalent to that for a physical lab, but the process happens in software that is controlled by the host workstation. Virtual models can be connected or disconnected in software, and can be configured to serve the specific DUT instead of connecting different pieces of hardware with cables as required by ICE.
This approach offers all the benefits of the virtual mode and adds an embedded testbench in the form of a target OS, drivers and applications running on a virtual machine on the host workstation.
While ICE supports a handful of engineers per emulator, Veloce VirtuaLAB provides access to hundreds, making much wider use of a valuable resource.
Let’s look at how Veloce VirtuaLAB can be applied to three illustrative use cases:
- Ethernet for networking applications
- HDMI for video/audio applications
- PCIe for PC interface applications
VirtuaLAB Ethernet for networking applications
The proliferation of the Internet of Things (IoT) has boosted demand for more powerful Ethernet switches with designs reaching into the thousands of ports and bandwidths around 400GPS.
In this example, Veloce VirtuaLAB Ethernet was used to verify an Ethernet switch design that included a 128-port interface and a variable bandwidth of 1/10/25/40/50/100/120/200/400 Gbps. The SoC size reached 700-million ASIC-equivalent gates.
Emulating the design in ICE mode would have required 128 Ethernet testers and 128 speed adapters, making the testing setup massive, messy, complex, unreliable and costly (Figure 1).
With Veloce VirtuaLAB Ethernet, Ethernet testers are modeled in software running on a Linux workstation connected to the emulator. The software model is an accurate representation of the physical tester, based on proven implementation IP.
This virtual tester includes an Ethernet Packet Generator and Monitor (EPGM) with the ability to configure GMII, XGMII, XLGMII, CGMII, CXGMII, CCMII and CDMII interfaces for 1G, 10G, 25G, 40G, 50G, 100G, 120G, 200G and 400G respectively (Figure 2).
Multiple Veloce VirtuaLAB instances can be bundled together across multiple workstations to support large port-count configurations using High Speed Link (HSL) cards to connect co-model channels from workstations to the emulator. This tightly integrated transport mechanism is tuned for wall clock performance and transparent to the testbench. Data plane emulation throughput scales linearly with the port count because of this parallel runtime and debug architecture.
The Veloce VirtuaLAB Ethernet aims to provide a fast, accurate and easy-to-use functional verification solution to bring complex Ethernet SoC designs to market on schedule. It provides a software-controlled environment for generating, transmitting and analyzing Ethernet packets to test Ethernet designs mapped inside an emulation system. It performs off-line analysis of the traffic, provides statistics, and supports several other fuctions.
Reconfiguring the virtual tester to perform various functions is done through remote access to a workstation, a stable and reliable piece of equipment less costly than a complex Ethernet tester with equivalent functionality. It has the ability to support multiple users concurrently in a large software development team.
Veloce VirtuaLAB HDMI for Video/Audio Applications
The High-Definition Multimedia Interface (HDMI) is a digital audio/video protocol. It transmits uncompressed video data and compressed or uncompressed digital audio data from an HDMI-compliant source device (e.g., a display controller) to a compatible computer monitor (e.g., video projector, digital television, or digital audio device).
Several versions of HDMI have been deployed since its initial release in 2003. Each version improved audio and video capacity, performance, resolution and color spaces, and newer versions added 4K, 3D, Ethernet data connection, and Consumer Electronics Control (CEC) extensions. The current 2.1 version is one of the most complex interface standards.
The Veloce VirtuaLAB HDMI is aimed at verifying advanced video/audio designs. It consists of two parts, a generator and a receiver.
The first part generates thousands of video/audio HDMI frames from multimedia files (e.g., avi, tiff, bmp, etc.) compliant with the HDMI 2.0 standard, and at resolution of up to 4K60fps with RGB 4:4:4 color space. This stream is directly fed into the DUT sitting in the emulator and exercises the video/audio processing of a pre-silicon design. The frame generation is fully automatic, saving on time-consuming manual work.
The second part captures the DUT’s output and feeds it into a graphical HDMI analyzer to verify the correctness of the multimedia output, providing quick feedback on the quality of the images.
The speed of emulation ensures that streams of thousands of 4K frames (input and output) are processed in an acceptable time (Figure 3).
Veloce VirtuaLAB PCIe for PC Interface Applications
The Veloce VirtuaLAB PCIe is a verification component for computing designs and is shown in the block diagram in Figure 5.
On the emulator side, a virtual PCIe PHY that is compatible with the physical PCIe PHY makes switching between the two straightforward, easy and safe. A Veloce Root Port model communicates with a virtual machine (e.g., a Quick EMUlator) running on a server hosting a Linux OS, via a PCIe transactor.
The VirtuaLAB PCIe enables applications to interact with the emulated DUT as if it were real silicon on the testbench.
VirtuaLAB includes a dedicated protocol analyzer. The protocol analyzer use mode is familiar to the designer community. The analyzer shown in Figure 5 disassembles all Data Link Layer Packets (DLLP) and Transaction Layer Packets (TLP), and supports many other statistical and tracing capabilities. A detailed GUI front end organizes this information into a single utility that has access across the entire PCIe stack. The analyzer is coupled directly to the VM PCIe stack to support extremely fast time-to-visibility (TTV) on all trace and analysis.
VirtuaLAB PCIe provides 100% visibility into all transactions between the host and the emulator.
VirtuaLAB PCIe enables development of software and drivers in parallel with the hardware. software and hardware architectures can be co-verified and confirmed early in the development cycle, requiring less re-coding. Functional software APIs can be tested using VirtuaLAB PCIe.
VirtuaLAB PCIe can be used in pre and post-silicon to reduce the development and maintenance load on the hardware and software teams.
The deployment of an emulation platform in virtual mode simplifies deployment, eases debug, improves debug accuracy, creates new applications for emulation, and broadens access to multiple concurrent users through remote access. Ultimately, the ability to move the emulator to the data center provides such an improvement in ROI that the virtual mode is increasingly replacing ICE.
The advantages of the virtual mode and the specific benefits offered by Veloce VirtuaLAB have boosted emulation platform productivity by an order of magnitude, enabling more test on shorter schedules. All this also helps to avoid silicon re-spins and reduce risk.