Expert Insights

If you're going to be working on any aspect of multicore embedded system design, a newly published book titled "Real World Multicore Embedded Systems" will be an excellent guide.

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.

Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.

How to speed project start-up, boost designer productivity and increase schedule predictability using design management tools.

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.

Better upfront analysis can help avoid propagating errors from RTL into the netlist, and reveal a number of ways to improve the quality of your final design.

Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.

Mind how you go. The only truly free thing about open source tools is the download itself. There is, however, a 'third way', matching professional support to these often useful options.