![](https://www.techdesignforums.com/practice/files/2019/11/www.maxpixels.net-Source-Code-Programming-Digital-C-Code-Coding-583537-150x143.jpg)
UPF
![](https://www.techdesignforums.com/practice/files/2019/11/www.maxpixels.net-Source-Code-Programming-Digital-C-Code-Coding-583537-150x143.jpg)
![Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.](https://www.techdesignforums.com/practice/files/2019/05/TomAnderson-150x150.jpg)
Achieving the interactive development of low-power designs
![](https://www.techdesignforums.com/practice/files/2019/02/featimg-150x130.jpg)
Low-power debugging made easy
![Rahul Chirania is a staff applications engineer with the static verification team at Synopsys.](https://www.techdesignforums.com/practice/files/2018/12/image_Rahul_Chirania-150-150x150.jpg)
Verifying clock domain crossings in UPF-based low-power SoCs
![Amol Herlekar, Synopsys](https://www.techdesignforums.com/practice/files/2015/10/Amol-Herlakar-64x64.jpg)
Preparing for low-power verification success: setting objectives and measuring outcomes
![Power switch](https://www.techdesignforums.com/practice/files/2015/08/tdf_switch_teaser-64x64.jpg)
‘Even the software guys are starting to talk in milliwatts’
![](https://www.techdesignforums.com/practice/files/2013/09/SNPS-TDF-UPF-hierarchy-pt-2-feat-img-64x64.jpg)
Managing power intent, signal isolation and level shifting in a UPF-based multi-voltage IC design
![](https://www.techdesignforums.com/practice/files/2013/09/SNPS-TDF-UPF-hierarchy-feat-img-64x64.jpg)
Choosing a block representation in a UPF-based hierarchical multi-voltage IC design
Extending UPF for incremental growth
Erich Marschner Accellera’s Unified Power Format (UPF) is in production use today, delivering the low-power system-on-chip (SoC) designs that are so much in demand. Building upon that success, IEEE Std 1801-2009 [UPF] offers additional features that address the challenges of low-power design and verification. These include more abstract specifications for power supplies, power states, and […]
UPF delivers on power
Long before the first portable computer batteries exploded, and even before anyone had the first visions of building massive data centers in the cold northwestern states of Oregon,Washington and Alaska, power consumption by electronic devices was a tough problem for chip designers. The difference now is that we are trying to manage power in ever-smaller […]
PLATINUM SPONSORS
![Synopsys Synopsys](https://www.techdesignforums.com/sponsors/files/2012/09/Synopsys_logo_268.jpg)
![Cadence Design Systems Cadence Design Systems](https://www.techdesignforums.com/sponsors/files/2013/01/cadence_logo_red.jpg)
![Siemens EDA Siemens EDA](https://www.techdesignforums.com/sponsors/files/2017/04/mentor-asb1.jpg)
View All Sponsors