UPF delivers on power

By Yatin Trivedi |  No Comments  |  Posted: December 1, 2007
Topics/Categories: EDA - Verification  |  Tags: ,  | Organizations:

Long before the first portable computer batteries exploded, and even before anyone had the first visions of building massive data centers in the cold northwestern states of Oregon,Washington and Alaska, power consumption by electronic devices was a tough problem for chip designers. The difference now is that we are trying to manage power in ever-smaller devices that demand more performance. And it is not just an issue of how long the battery will last in your mobile phone, music player or video game. The problem and its solutions have far-reaching implications affecting everything from heat dissipation and cooling to package design and power-aware software control. This multi-faceted problem requires a multifaceted, well-integrated solution.

As solution providers to the chip and system design industry, EDA vendors have long been researching many innovative approaches to power management, resulting in a host of design verification, implementation and analysis tools. Of late, finding those solutions has required a three-way collaboration between the chip design, semiconductor process and manufacturing, and EDA communities. The designers have come up with many clever approaches for ‘gating’ the design’s clock and power so it operates only when necessary.

The process developers have created special processes to operate digital logic at different threshold voltages and developed various power-saving structures. And the EDA vendors have provided the design tools that bring these process and design techniques together.


Figure 1. UPF usage spans the entire design flow, from RTL to GDSII.

Unfortunately, up until now it was left to the designers to create a consistent flow across all phases of the design using only a set of ‘features’ in the tools that resembled a bag of tricks. Clearly there has long been a need to address power management across many aspects of design for high-volume consumer products manufactured in advanced 65 and 90nm processes. Recently, things have changed for the better.

In 2006, many leading designers and process (library) developers demanded that the EDA industry collaborate on creating a power management standard. Besides the obvious interoperability required for implementing this standard in various tools, additional and equally important requirements were identified to ensure that the standard was developed and made accessible to the entire industry in an open and inclusive manner.

New standard takes shape under Accellera

A technical committee consisting of designers of mobile, automotive, storage and consumer applications, and all the leading EDA vendors, was assembled under the aegis of Accellera, the respected standards organization, to develop this new low-power standard. The reason for forming this particular committee under Accellera was an obvious one:

Accellera has developed and delivered several widely adopted standards – including Verilog, SystemVerilog, PSL,OVL and OCI – and has successfully transferred themto the IEEE’s worldwide standardization process. Accellera also offers a very open and inclusive process under which technical work takes place.

In developing the new low-power standard, this openness was clearly evident. The participants faced no restrictions such as licensing, membership or annual fees. As for inclusiveness, eight donations of proven technology were made from seven companies and every donation was considered by the committee in order to develop the base for this standard. No one donation was treated exclusively or required others to be force-fit into a specific use model. Considering that the technology donations came from multiple participants and that many concepts as well as commands were assimilated into one cohesive format, the low-power standard was aptly called the Unified Power Format (UPF).

Because each participating company also put in considerable effort and resources, UPF was developed in less than six months, defying the skeptics who warned against a slow-as-molasses standardization process.

Accellera and the UPF committee also worked closely with the IEEE. The resulting UPF standard has now formed the foundation of IEEE project 1801 (P1801), which is well on its way to ratification. Not only does the industry now have a low-power standard, but it also has a roadmap through IEEE P1801 for further development and broader adoption.

Company Product Usage Email Contact
Atrenta Spy Glass-Power Analysis upf@atrenta.com
Axiom MPSim Verification upf@axiom-da.com
Azuro PowerCentric Implementation upf@azuro.com
Magma Talus Power Implementation upf@magma-da.com
Magma Quartz Rail Analysis upf@magma-da.com
Mentor Questa Verification upf@mento.comr
Mentor FormalPro Verification upf@mentor.com
Springer LPMethodology Manual How-to Book Carl.Harris@springer.com
Synopsys MaVeric ArchPro Verification upf@synopsys.com
Synopsys DesignWareIP IP blocks upf@synopsys.com
Synopsys VCS Verification upf@synopsys.com
Synopsys Design Compiler Ultra Implementation upf@synopsys.com
Synopsys Power Compiler Implementation upf@synopsys.com
Synopsys DFT Compiler/MAX Implementation upf@synopsys.com
Synopsys Leda Analysis upf@synopsys.com
Synopsys Formality Verification upf@synopsys.com
Synopsys IC Compiler Implementation upf@synopsys.com
Synopsys PrimeTime/PX,SI Analysis upf@synopsys.com
Synopsys PrimeRail Analysis upf@synopsys.com
Synopsys TetraMAX Implementation upf@synopsys.com
Virage Silicon Aware IP Low Power Libraries upf@viragelogic.com

Figure 2. UPF solutions at-a-Glance

What is UPF?

Written in TCL, UPF describes the low-power intent for design implementation, analysis and verification. It captures the lowpower design specification from RTL to GDSII, with consistent language throughout the design and verification flow. UPF allows designers to use open, multi-vendor tool flows for low-power silicon design. A UPF specification defines how to create a network to supply power to each design element, how the individual supply nets behave with respect to one another, and how the logic functionality is extended to support dynamic power switching to these logic design elements. By controlling the operating voltages of each supply net and whether the supply nets (and their connected design elements) are turned on or off, the supply network only provides power to the functional areas of the chip needed to complete the computational task in hand in a timely manner.

Combined with the design’s RTL, the UPF file is the input to several tools (e.g., simulators, synthesis tools, formal verification tools and place and route tools (Figure 1)).

Synthesis tools can read the RTL and UPF design input files and produce a netlist, and the UPF file may be reused without change later in the tool flow. A UPF-aware logical equivalence checker can read the full design files and perform checks, including the results of the UPF commands, to ensure equivalence. Place and route tools read both the netlist and UPF files and produce output, potentially including an output UPF file to account for changes in hierarchy or other transformations.

Power design intent can be easily specified over many elements in the design. A UPF specification can be included with the other deliverables of intellectual property (IP) blocks and reused along with the other delivered IP files.

True interoperability

In June 2007, seven EDA companies announced that they provided or would provide UPF-compliant tools: Atrenta, Axiom, Azuro,Magma Design Automation,Mentor Graphics, Synopsys and Virage Logic. A how-to guide, the Low Power Methodology Manual, has been published by Springer, is available at www.springer.com, and has its own website (www.lpmm-book.org). Having seen the success and popularity of UPF, even more EDA companies are working on their own specific solutions within the standard today.

Underlining the common ground that rival vendors have found around the UPF standard, Figure 2 lists the tools announced back in June that deliver UPF support. Early versions of these products were also demonstrated at June 2007’s Design Automation Conference (DAC) in San Diego, and putative users can continue to investigate these tools by contacting the relevant companies. Meanwhile, the standard itself is openly and freely available to download at www.accellera.org/activities/p1801_upf/.

UPF is a robust, flexible standard that addresses designers’ needs throughout the design cycle, allowing them to mix and match tools and flows from various vendors. A prime example of how fiercely-competing companies can still work together for the common good of the industry, UPF is now ready for users who need to focus on low power for their complex ASICs and SoCs. Although some EDA vendors may debate about the superiority of certain proprietary solutions – and the accompanying formats – there remains a prevailing opinion in the design community that an open standard is needed to enable interoperability between tools from multiple, competing EDA vendors. UPF has successfully achieved this goal.

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