May 28, 2015
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
October 31, 2013
X propagation within RTL simulations can hide fatal bugs. Uncovering and eliminating the effect improves design quality and avoids respins.
July 19, 2013
How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis
October 23, 2012
The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
March 20, 2012
Logic glitches in asynchronous clock domain crossing paths can arise even when synthesis tools declare a design’s RTL and gate-level netlists equivalent. This article describes Real Intent’s approach to capturing them.