Keeping high-speed designs clean with ERC
Electrical rule checks (ERC) are now available to deal with increasing PCB design complexity, speed project delivery and protect the intellectual property within them.
signal integrity
Overcoming increasing PCB complexity with automation
Advanced PCB and IC technologies have to be matched with advanced design and analysis tools if companies are going to produce board designs that are right first time, on time.
Designing a PCB for power integrity
Signal integrity (SI) issues have been around for a while, the result of ever-faster edge rates. Both SI and PI problems manifest themselves as data errors. Indeed, PI problems are often misdiagnosed as SI problems. As such, an understanding of power delivery issues is essential to the success of any board project, as is a [...]
Reducing system noise with hardware techniques
Circuit noise problems can originate from a variety of sources. By carefully examining attributes of the offending noise you can identify it’s source, thereby making noise reduction solutions become more apparent. There are three subcategories of noise problems: device, conducted and radiated noise. If an active or passive device is the major noise contributor, you […]
Board-level timing analysis
This paper builds on “Timing Numbers In ICX – What do we do with them?” [1]—a paper presented at the 2006 Mentor Graphics User2User conference (and now available for download at the journal’s Web site, www.edatechforum.com). The original paper focused on the need for timing analysis and the theory behind it; this paper takes a […]
Multi-corner multi-mode signal integrity optimization
Signal integrity (SI) is an ever-growing problem as more interconnect effects and fast clocks increase the chances of crosstalk noise and glitches as well as unexpected signal delays. There has been a significant increase in SI-related timing violations due to the increasing influence of lateral wire capacitance in designs at 65 and 45nm. A fast-increasing […]