Catch the next wave in DFT automation
It is easier than ever to build a flexible, resilient, and end-to-end hierarchical DFT flow with smart automation.
EDA
Don’t get lost in the cloud
Mentor is rolling out an comprehensive cloud-based design infrastructure feeding into digital twin strategies.
How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R
A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
UVM coding guidelines offer clarity in a complex world
These 13 suggestions toward best practice address some of the most persistent challenges with the Universal Verification Methodology.
VHDL users also deserve efficient design and verification
More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.
Covid-19 rings changes for virtual working
Virtualization is becoming ever more common during the Covid-19 outbreak, even for complex technologies like emulation, and showing its strengths.
How to use runtime monitoring for automotive functional safety
The promise of autonomous vehicles is driving profound changes in the design and testing of automotive ICs.
How cloud computing is now delivering efficiencies for IC design
A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.
Keep chip designs on the level with CMP simulation and dummy fill optimization
This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.
Security: Making the unknown, known
How to combine formal and dynamic verification within an app to uncover security vulnerabilities.