Nangate

August 23, 2011

Addressing SoC performance challenges in advanced deep-submicron CMOS processes

The article describes a novel optimization approach that extends leading methodologies to improve performance, power and area. It is based on a pre-generated cell library that extends commercially available foundry libraries and couples it with novel logic optimization to aim for the delivery of near full-custom performance levels. The approach assesses the gate-level netlist generated [...]
Article  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:

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