EDA

This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.

Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.

Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.

Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.

Designers need to understand how the architecture of electronic control units used to implement ADAS in vehicles is changing.

Doc Formal sets out the 10 cost points in verification that formal will help you control and reduce.

Choosing the right crypto processor implementation involves a complex set of design tradeoffs between speed, area, power consumption and flexibility. Using consistent benchmarks can help explore your options.

A hierarchical methodology removes DFT from the critical path for large designs. The methodology is compatible with other techniques such as channel sharing, which can further reduce ATPG turn-around time and test cost.

An evolution of the Ethernet standard enable time-sensitive networking with the predictable latencies and guaranteed bandwidth necessary for automotive applications.

How to use formal fault pruning, injection and sequential equivalency checking to meet the FMEA analysis requirements of the functional safety standard.