Chipmaker

The next boost to verification productivity will come from the integration of multiple strategies and tools.

The fourth installment discusses the extra levels of debug capability available when using virtual prototypes through the example of an ARM big.LITTLE-based embedded system.

How Marvell used an enhanced ECO tool flow for SoC design to cut overall time-to-timing-closure by nearly 70%.

Better delay estimation of sub-32nm interconnects, in which resistivity varies up to 100x between layers, helps Cavium improve overall performance and get ready for even denser processes

The first in a series of articles about using virtual prototyping techniques to achieve more effective debug.

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows

How the company migrated to an OVM-based methodology to design and verify a 30 million-gate ASIC design, on the path to UVM.

How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis

The chipmaker used Calypto’s PowerPro to carry out power analysis of its latest core design at the RTL rather than at post-gate synthesis.