Real Intent’s Ascent XV at the ‘fuzzy’ boundary between design and verificiation
Upgrade to Ascent XV X-propagation and reset optimization tool claims 10X runtime gain, deeper reporting, further integration with Verdi and more.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
NI uses complex RF to help attack software development
A massive MIMO processor being developed at Lund Unversity is serving as a testbed for a platform view that National Instruments is building for LabView.
The 1ms difference for embedded systems
What’s in a millisecond? The difference between today’s embedded systems and tomorrow’s, Professor Gerhard Fettweis of TU of Dresden said at DATE 2014.
Synopsys begins IC Compiler II roll-out
New data model and optimisation strategy, plus revised analysis engines update Synopsys’s IC Compiler place and route tool
Mentor buys BDA for AMS portfolio
Mentor Graphics has bought Berkeley Design Automation (BDA), a specialist in analog, mixed-signal, and RF circuit verification using FastSpice.
ADC design shifts gears for lower power
SAR analog-to-digital converters promise better energy efficiency for a growing range of designs, as S3 Group has found.
Mentor begins to take wraps off Xpedition PCB software overhaul
New-look Xpedition flow launches with preview of layout features including better control over automation, 2D/3D views, and a UI even for ‘casual’ users.
Memory focus for specialized 32bit MCU
For a new 32bit microcontroller family, FTDI Chip has decided to not follow the crowd into the ARM camp but go it alone with its own proprietary architecture
Multicore Association prepares standard for modelling parallelized software
The Multicore Association is getting close to publishing the first version of a specification that aims to standardise the way processor designers can describe the available parallelism
Visual timing tool focuses on high-speed PCB signals
Cadence Design Systems has developed a visual timing analyzer for Allegro that tunes signals used by high-speed protocols such as DDR4, PCI Express, and SATA.