Synopsys

September 18, 2014

Using optimized design flows to meet PPA goals for SoC processor cores

How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.
September 2, 2014
Intel's trigate is among the structures to be modeled by the revised BSIM4

Design enablement and entitlement for 14/16nm finFET processes

How EDA tools are evolving to make it possible to design with finFET processes.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , ,   |  Organizations: , ,
August 27, 2014
Prasad Saggurti is the product marketing manager for embedded memory IP at Synopsys.

Six key criteria for deciding to migrate to a finFET process

Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Expert Insight  |  Topics: EDA - IC Implementation, IP - Selection  |  Tags: , ,   |  Organizations: , , , , ,
August 19, 2014
ZeBu server

Hybrid emulation for development, validation and verification

This article introduces hybrid emulation, a combination of emulation and virtual prototypes, and its application to tasks such as architecture validation, early software development and software-driven verification.
July 25, 2014
Steven Cline is a senior design automation Manager at Altera’s Austin Technology Center, focusing on design-flow automation for traditionally placed and routed blocks and custom FPGA IP used on Altera’s advanced FPGA products.

Using standardized design flows to cut time to tape-out – and speed design-flow evolution

Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
Expert Insight  |  Topics: IP - Design Management, EDA - IC Implementation  |  Tags: , , , ,   |  Organizations: , ,
July 20, 2014
Rebecca Lipon is the senior product marketing manager for the functional verification product line at Synopsys. Prior to joining the marketing team, Rebecca was an applications engineer at Synopsys working on UVM/VMM adoption, VCS, VIP, static and formal verification deployments.

Rethinking SoC verification

The argument for an integrated approach to SoC verification
July 9, 2014
Car cutaway

Using Ethernet in automotive networks

Will Ethernet become the dominant interconnect for automotive applications? A look at the market trends and standards, and how to use Ethernet IP and virtual-prototyping solutions in automotive applications.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , , , , , ,   |  Organizations:
June 27, 2014

How to use PCI Express in low-power mobile SoCs by exploiting M-PCIe

How to use PCIe in low-power SoCs by swapping the standard PCIe PHY for M-PCIe, defined by MIPI for mobile use
Article  |  Topics: EDA - IC Implementation, IP - Selection  |  Tags: , , , ,   |  Organizations:
May 24, 2014
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Prototypers get faster route to first clock tick

ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
Expert Insight  |  Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: , ,   |  Organizations:
April 28, 2014

Overcoming the power/performance paradox in processor IP

The configurability of processor IP such as Synopsys' ARC HS family gives designers the option to optimise for power, performance or a combination of both.
Article  |  Topics: IP - Selection  |  Tags: , ,   |  Organizations:

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