How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.
How EDA tools are evolving to make it possible to design with finFET processes.
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
This article introduces hybrid emulation, a combination of emulation and virtual prototypes, and its application to tasks such as architecture validation, early software development and software-driven verification.
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
The argument for an integrated approach to SoC verification
Will Ethernet become the dominant interconnect for automotive applications? A look at the market trends and standards, and how to use Ethernet IP and virtual-prototyping solutions in automotive applications.
How to use PCIe in low-power SoCs by swapping the standard PCIe PHY for M-PCIe, defined by MIPI for mobile use
ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
The configurability of processor IP such as Synopsys' ARC HS family gives designers the option to optimise for power, performance or a combination of both.
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