Thanks to today’s emerging technology nodes, we can put more than a trillion transistors on a single 300mm wafer – more transistors per wafer than there are stars in the Milky Way. By the end of the decade, we should be able to put more than a trillion transistors on a single die, and 10 trillion by the end of the next.
Our ability to keep printing more devices in the same area creates opportunities for staggering amounts of functional integration – yesterday’s leading-edge DSP chip can now be found tucked into a corner of a mobile baseband chip almost as an afterthought, surrounded by functionality that would have been spread across multiple chips and PCBs when the DSP was invented.
The EDA industry plays a key role in enabling continuing integration, developing tools and methodologies that allow designers to organize huge amounts of functionality into a coherent design, verify that it is correct and then implement it in an increasingly complex physical context. It’s easy to believe, therefore, that it is only the most advanced designs, manufactured on emerging technology nodes, which need the most advanced tools.
That’s not true. Only a small yet shrinking number of applications fulfil the economic requirements of emerging technology nodes. However, there are plenty of opportunities at the established technology nodes; there are plenty of applications that don’t (won’t) benefit from the emerging technology nodes, and yet are advanced by design. Automotive is one of them.
Think of your car – the chips in the driver’s smartphone will be made on 16nm or 14nm processes, but the increasingly sophisticated engine and powertrain control, suspension, steering, braking, safety, comfort and entertainment systems are more likely to be built on established technology nodes, such as 90nm. They’ll combine digital, analog and mixed-signal circuits with embedded SRAM, non-volatile memories, and perhaps even MEMS sensors. The chips will integrate all this functionality – and yet still meet the stringent safety, reliability, quality, cost and time-to-market requirements of the automotive market.
In this context, it’s design, not process, which provides the greatest differentiator. Automotive IC designers have the same, or perhaps an even greater, need to access the most advanced EDA and design techniques as their smartphone and tablet IC colleagues.
What challenges do they face? Automotive ICs are rarely plain-vanilla CMOS and are seldom digital-only. Supply voltages can range from one to several tens of volts. Operating conditions, such as vibration, humidity and temperature, are extreme. Complex floorplans and design hierarchies, in which digital functionality is no longer the overriding concern, create implementation and verification issues. And the resultant chips cannot fail without handling the resultant errors properly.
A typical advanced automotive chip design needs high performance, yet must operate at low power to avoid adding to the growing burden on the vehicle’s battery. CMOS circuitry only has a minority share of the die area, and is often completely surrounded by bipolar analog and high-voltage DMOS. The chip’s floorplan is usually driven by the requirements of the analog functions, leaving the digital functions to fit where they can. Routing resources on chip have to be used efficiently. And the design process needs to enable the digital, analog and mixed-signal blocks to be developed alongside, and in step, with each other.
How do advanced tools help ease automotive design and improve quality of results?
In some cases, advanced tools can enable designs that would have been somewhere between ‘very difficult’ and ‘impossible’ to finalize using the tools available when the manufacturing processes upon which they are built were devised.
For example, a recent 180nm power controller IC featured 12 voltage islands, and was only possible because it was designed using tools and techniques first developed to reduce power consumption in 65/45nm mobile ICs .
Here’s another spill-over from advanced-node techniques. When we reached the 20nm node, we needed to split the most critical layers so they could be patterned using separate, less dense masks. The arrival of double-patterning lithography demanded innovations in routing, and these advances are now enabling much denser automotive implementations with greater routing utilization, fewer routing layers, and greater use of double vias, for lower cost and increased reliability.
Tool integration is also making it easier to develop sophisticated automotive ICs. For example, it is difficult to develop reliable power and ground networks for automotive ICs because of their complex floorplans. The ability to analyze the power and ground network in detail, without leaving the main design flow, helps detect potential issues as early as possible.
Advanced tools and methodologies also help on the verification side, where complex analog, digital, mixed-signal and even electromechanical behaviors must be verified standalone, and in their shared context, for their functionality and impact upon safety and reliability requirements.
Automotive designers also benefit from advanced verification tools that offer excellent point-tool facilities and performance, and which fit within an overall vision for enabling verification almost from design conceptualization through to detailed circuit simulation and sign-off. This verification continuum draws tools as diverse as SPICE simulators, formal checks and FPGA prototyping into a consistent environment as needed.
Emerging technology nodes have always demanded advanced tools, but as the characteristics of the leading digital CMOS processes converge it is clear that product differentiation will increasingly have to come from design. Those markets whose chips are built on established technology nodes have always known this and acted accordingly. Today, though, designers working in these sectors can apply the most advanced tools and techniques to achieve better designs.
Marco Casale-Rossi is a senior staff product marketing manager in the Design Group at Synopsys, responsible for researching the impact of semiconductor technology innovations on EDA tools, methodologies and flows, and creating the technical foundations and contents of presentations relating to advanced IC design implementation. Casale-Rossi also contributes to the development of Synopsys’ vision of the nanometer design and technology roadmap.
Company infoSynopsys Corporate Headquarters 690 East Middlefield Road Mountain View, CA 94043 (650) 584-5000 (800) 541-7737 www.synopsys.com
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