The testiest place on earth

By TDF |  No Comments  |  Posted: August 23, 2011
Topics/Categories: EDA - DFT  |  Tags:

But in a good way. As ITC moves to Anaheim’s Disneyland in September, we preview the 2011 edition.

This year’s International Test Conference (ITC) and all the related IEEE Test Week activities are moving to a new venue and, perhaps more significantly, a new time. Usually held in late fall, ITC 2011 will take place from September 18th-23rd at the world famous Disneyland Hotel in Anaheim, California.

ITC is, as the blurb declares “the world’s premier conference dedicated to the electronic test of devices, boards and systems—covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement.

“At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers and test engineers.”

With that in mind, we can only breeze through a few of the highlights here. The full program can be found on the conference website at, along with currently available registration packages.

Key themes


This year’s conference will reflect the ever increasing importance of analog/mixed signal (AMS) design for test (DFT) with a dedicated session on each day of the conference.

A highlight paper in ‘New DFT for General Analog’ (Session 1, Tuesday, 9/20/11, 2.00pm-3.30pm) describes how engineers at NXP Semiconductors developed a novel, fast fault-simulation method that produced a 50 percent time reduction maintaining zero defect quality on a volume project.

The Wednesday (9/21/11, 8.30am-10.00am) AMS session, ‘RF DFT and Test Cost Reduction’, addresses one of the most practical challenges facing today’s design projects. Papers here include a joint Intel-Infineon Technologies presentation on how a low-cost digital automated test equipment strategy was created for a transceiver developed at four different locations.

The cutting edge is explored on Thursday (9/22/11, 10.30am-12.00pm) in Session 16, with two papers on new sampling methods for analog signals. Contributors include Advantest and Texas Instruments.

Diagnosis and data mining

Session 15 (Thursday, 8.30am-10.00am) looks at how the increasing complexity of today’s failure modes means that practitioners must increasingly look to what they can extract from ‘real world’ data as opposed to test chips and structures. 

In the first of the three featured papers, a Texas Instruments team will show how it was able to dynamically control test flows and content using continuous per-die updates of test fail rates using Bayesian statistics.

Then, engineers from Freescale Semiconductor will describe how they have been able to predict potential failures using the binary classification and outlier analysis of wafer test statistics.

Finally, Infineon and EDA partner Mentor Graphics will describe a fast simulation-based method for diagnosing single or multiple IDDQ failures in digital logic, verified on real silicon.

Meanwhile, Session 9 (Wednesday, 10.30am-12.00am) discusses the latest techniques developed to “analyze and detect ever more subtle failure mechanisms including small delay defects, those related to statistical variations in lithography and those subject to enhanced screening using body bias control during test.”

Defect-oriented and power-aware ATPG

One inevitable result of increasing complexity is the increasingly subtlety of the type of defect that now has to be identified. And, of course, the allied trend toward more sophisticated forms of investigation leaves test prey to the Law of Unintended Consequences—could some of today’s DFT be doing more harm than good? On Tuesday, Session 2 (2.00pm-3.30pm) presents three papers that address these challenges.

The first paper, from the University of Stuttgart, introduces the concept of P-PET—partial pseudo-exhaustive test. Already, an embedded test tends to comprise a pseudo-random element followed by a deterministic one to improve coverage. The P-PET concept seeks to make the pseudo-random part more effective so that you can shorten the deterministic part.

The second paper, from the Nara Institute of Science and Technology, seeks to identify small delay faults using faster-than-at-speed test techniques. According to the official ITC preview, “This is accomplished by copying patterns and running them at desired speeds, masking the ends of paths which would have timing failures due to the increased speed. It shows how to minimize slack and maximize delay for the paths that are left. This increases defect coverage while reducing the number of patterns.”

The third paper, from National Taiwan University and the Kyushu Institute of Technology, looks at an ongoing challenge in reducing power consumed during scan test to protect circuits and guarantee accurate results. “Independently,” the program adds, “we must reduce power consumption in the functional model, often through clock gating. These requirements have been in conflict, and we typically turn off clock gating during scan. This paper shows how to make use of existing clock gating hardware to reduce power usage during the launch cycle of an at-speed test.”

There are many more focus areas for the program, reflecting both traditional and emerging areas of interest and branches of test technology. In the run-up to the conference, ITC is itself publishing further session previews on its website.


Panel sessions are the lifeblood of many a conference, pushing the latest thinking and ideas into the open for peer scrutiny and discussion. They also are one way in which many attendees seek to drag out of their suppliers those products and concepts reaching fruition in the lab.

There are four panel sessions scheduled for ITC 2011.

The opening ‘Industry Leaders’ panel (Monday, 4.30pm-6.00pm) addresses the key question, ‘How will testing change in the next 10 years?’

Moderator and organizer Phil Nigh has already flagged a number of key questions for the participants (What is the biggest problem in the industry that gets little discussion? How will the requirements for ATE change in the next 10 years? How will fundamental design-for-test requirements change? What is the best area for creating a new business in the ‘test field’? Will design reconfiguration at test or new adaptive test applications change how we test? End-to-end testing (wafer probe through field) will we develop methods to truly optimize across all steps?)

He will also be seeking ideas from the audience to put to a line-up that includes executives from LTX-Credence, Nvidia, Cisco Systems, Synopsys, GlobalFoundries, Mentor Graphics and AMD.

The second panel (Tuesday, 4.00p.m-5.30pm) will address ‘Challenges and best practices in advanced silicon debug. Among various topics, it will explore the future use of concepts and strategies such as structural-based test, and how they are poised to assume a still greater role in debug and power analysis. It will also consider the advantages and disadvantages of system test versus structural test for validation.

On Wednesday (10.30am-12:00pm), the third panel is looking to stir up a “good honest discussion” about the future of in-circuit test (ICT), under the banner ‘The King is dead—long live the King!’

The primary contention is whether the current ICT infrastructure is sufficient to meet the demands of next-generation printed circuit board assembly (PCBA) challenges, and if not, where it is deficient. And to discuss that, the organizers are assembling a line-up that represents all branches of the user/manufacturing community as well as the ICT suppliers.

The fourth panel (Thursday, 2.00pm-3.30pm), will look at one of the fundamental shifts taking place in not just electronics but industry generally. ‘The Gap: test challenges from the Asia manufacturing field and today’s tools’ directly addresses the challenges arising as more assembly moves into countries such as China. According to organizer X. Gu of Huawei Technologies, “By presenting the gap between the test challenges that the Asian companies are facing and the tools they have available today, we hope to give the ITC community an opportunity to better understand the needs for innovation in test technologies and tools.”


This year’s ITC features a typically broad array of headline speakers. The formal opening session on Tuesday morning (9.00am–10.30am) will feature Bill Dally, chief scientist with Nvidia speaking to the topic of ‘Power, programmability and granularity: the challenges of exascale computing’.

Exascale computing is seen as the key to future performance when we enter the third decade of the 21st century and, Dally will argue, it will demand innovation chiefly in three areas: power efficiency, programmability and execution granularity.

“To build an exascale machine in a power budget of 20 MW requires a 200-fold improvement in energy per instruction: from 2 nJ to 10 pJ. Only 4X is expected from improved technology. The remaining 50X must come from improvements in architecture and circuits,” Dally notes in his abstract.

“To program a machine of this scale requires more productive parallel programming environments, ones that make parallel programming as easy as sequential programming is today. Finally, problem size and memory size constraints prevent the continued use of weak scaling, requiring these machines to extract parallelism at very fine granularity, down to the level of a few instructions.”

The second conference keynote (Wednesday, 4.30pm-5.30pm) is sure to secure a full house. If there is one business that matches semiconductors for secrecy, it is theme parks. The way in which rides and attractions are developed depends on surprising both your customers and your rivals—and no one is better at that than this year’s ITC host location, Disneyland.

The keynote speaker Chuck Davis is senior technical director with Disney Creative Entertainment and he will specifically focus on the World of Color show, performed nightly in the neighboring Disney’s California Adventure theme park (and which ITC delegates will also have a chance to see in a private viewing during the conference’s Welcome Reception).

Davis will describe the design, fabrication, installation and mounting process for the attraction and how it is achieved using a great deal of off-the-shelf technology as well as imagination.

The final keynote (Thursday, 1.00pm-2.00pm) will also take the audience inside what is, in the U.S., another influential (but also comparatively little-known) organization. Jyuo-min Shyu, who recently became president of Taiwan’s Industrial Technology Research Institute (ITRI), will offer ‘A systems perspective on the R&D of industrial technology’.

“The process of translating scientific discoveries into technologies involves a series of risk steps, resulting in low success rates,” his abstract says. In industrial technology research institutes such as ITRI, the planning of such projects typically starts with conceptualizing innovative applications that meet certain needs of consumers or society. Once initiated, the process is forced to be in constant touch with both ends of its range: scientific discovery and market needs; the utmost consideration is the large impact it will have on industries, economy and the society at large.”

The keynote will look at this strategy in terms of semiconductor research examples, collaboration models between industry and academia, and the role of directing projects so that the results take proper account of cost, quality and reliability.

Many details of the 2011 ITC program were still to be finalized as this issue of Tech Design Forum went to press. The organizers are also providing further thematic focus articles on different sessions as the event approaches. So, for the most up to date view of what’s already shaping up to be a lively conference, go to

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors