Real Intent state machine debug focuses on core errors
Real Intent' Ascent IIV tool adds analysis functions to pinpoint fundamental errors in finite state machines and support for SystemVerilog 2009.
Author Archives: Chris Edwards
IoT calls for security rethink, says Green Hills CTO
The rise of the Internet of Things will drive a change in attitude to security, Green Hills CTO David Kleidermacher claimed in his Embedded World keynote.
Cadence uses SQL to boost verification manager capacity
Cadence Design Systems has launched Incisive vManager, a verification management tool that uses a database backend to manage coverage on large SoC projects.
MIPS brings virtualization and tamper protection to 32bit MCUs
Imagination Technologies' MIPS group has launched processor cores that include support for virtualization and measures to prevent reverse engineering.
DVCon sets up in Europe
Verification conference DVCon is expanding into Europe with a two-day conference and show at the Hilton in Munich, Germany.
Capacity may force uptick in chip prices, says analyst
Chip pricing could see a significant uptick because of reduced investment in fab capacity, according to Future Horizons.
Power analyzer pulls in scope functions for energy-saving designs
Yokogawa has pulled together power meter and oscilloscope functions into a hybrid instrument for teams working to increasingly stringent energy-usage regulations.
Cadence updates Incisive with formal, CRV, wreal additions
Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
Inside Secure to offer IP for mobile hardware vaults
Inside Secure has developed a set of certification-ready hardware IP modules that can be used stand-alone or in conjunction with ARM's TrustZone
Complexity to force shift to four-stage verification
The complexity of on-chip interconnect and the relentless growth in software size will drive the move to a four-stage verification process as well as the increased use of formal techniques to speed up SoC-level testing, Mentor Graphics verification specialist Mark Olen claimed at the Verification Futures conference.